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Pull requests list

Verilog: clean up expression construction cleanup Verilog
#1360 opened Oct 23, 2025 by kroening Loading…
1
SMV: enums are global SMV
#1358 opened Oct 23, 2025 by kroening • Draft
Verilog: fix semantics of cover disable iff Verilog
#1346 opened Oct 20, 2025 by kroening • Draft
SMV: implement bit selection operator SMV
#1305 opened Oct 9, 2025 by kroening • Draft
Generate VCD file for each cover statement
#1296 opened Oct 3, 2025 by ShashankVM Loading…
1
10
SystemVerilog .* wildcard port connections Verilog
#1240 opened Aug 26, 2025 by kroening • Draft
SMV: union operator SMV
#1186 opened Jul 7, 2025 by kroening • Draft
split up ltl_sva_to_stringt::rec cleanup engines
#1171 opened Jun 27, 2025 by kroening • Draft
SVA: strengthen typing of sva_sequence_concatenation_exprt cleanup
#1161 opened Jun 17, 2025 by kroening • Draft
1
NeurIPS 2025 SystemVerilog benchmarks
#1147 opened Jun 6, 2025 by kroening Loading…
SMV: bit selection operator SMV
#1113 opened May 18, 2025 by kroening • Draft
SMV: expression typechecker now post-traversal SMV
#1040 opened Mar 28, 2025 by kroening Loading…
2
SVA monitor engines Verilog
#1011 opened Feb 25, 2025 by kroening • Draft
SystemVerilog: interface instantiation Verilog
#972 opened Feb 6, 2025 by kroening • Draft
SystemVerilog: declarations in named blocks in tasks/functions Verilog
#970 opened Feb 6, 2025 by kroening • Draft
1
SystemVerilog: preserve scopes between compilation units Verilog
#963 opened Feb 4, 2025 by kroening • Draft
SystemVerilog: create identifier expressions in scanner Verilog
#953 opened Jan 29, 2025 by kroening • Draft
Add chipsalliance/sv-tests to CI
#939 opened Jan 17, 2025 by kroening • Draft
vlindex: fix parsing for constraint_block
#924 opened Jan 6, 2025 by kroening • Draft
SystemVerilog: fix identifier on enum type Verilog
#919 opened Jan 2, 2025 by kroening • Draft
liveness engine engines
#915 opened Dec 29, 2024 by kroening • Draft
SMV: clean up parse tree SMV
#909 opened Dec 27, 2024 by kroening • Draft
SMV: typechecking for ?: SMV
#906 opened Dec 26, 2024 by kroening • Draft
SystemVerilog: type parameter ports Verilog
#842 opened Nov 21, 2024 by kroening • Draft
Verilog: lowering for four-valued zero-extend Verilog
#796 opened Nov 1, 2024 by kroening • Draft
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