Skip to content

Verilog: extend static_cast3 test #1365

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Oct 29, 2025
+6 −2
Merged

Verilog: extend static_cast3 test #1365

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 6 additions & 2 deletions regression/verilog/expressions/static_cast3.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,11 +1,15 @@
module main;

typedef bit [7:0] eight_bits;
typedef bit unsigned [7:0] unsigned_eight_bits;
typedef bit signed [7:0] signed_eight_bits;

// 1800-2017 6.24.1
// "the cast shall return the value that a variable of the casting type
// would hold after being assigned the expression."
// Hence, this is an assignment context.
initial assert(eight_bits'(1'b1 + 1'b1) == 8'd2);
initial assert(unsigned_eight_bits'(1'b1 + 1'b1) == 8'd2);
initial assert(unsigned_eight_bits'(1'sb1 + 1'sb1) == 8'b11111110);
initial assert(signed_eight_bits'(1'b1 + 1'b1) == 8'd2);
initial assert(signed_eight_bits'(1'sb1 + 1'sb1) == 8'sb11111110);

endmodule
Loading