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The netlist engine now ignores various Verilog symbols that do not translate into circuitry, e.g., properties, sequences.

The netlist engine now ignores various Verilog symbols that do not translate
into circuitry, e.g., properties, sequences.
@kroening kroening marked this pull request as ready for review October 26, 2025 20:02
@tautschnig tautschnig merged commit f5276fe into main Oct 29, 2025
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@tautschnig tautschnig deleted the property_and1-aig branch October 29, 2025 08:21
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3 participants