Verilog: KNOWNBUG test for unconnected module input ports #1322
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tautschnig
reviewed
Oct 15, 2025
| --bound 0 | ||
| ^EXIT=0$ | ||
| ^SIGNAL=0$ | ||
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Would you mind adding a sentence stating what is going wrong here?
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tautschnig
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Oct 15, 2025
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