C++ Software Engineer · Ultra Low-Latency · HFT Infrastructure

I engineer ultra low-latency trading systems in C++20/23 on Linux. Every design decision is driven by one constraint: latency. No exceptions. No virtual dispatch. No heap allocation in the critical path.

• Lock-free concurrency — SPSC/MPMC ring buffers, cache-line padding against false sharing, wait-free progress guarantees
• CPU-level optimization — cache-line aware data layout, SIMD/AVX vectorization, branch prediction control, prefetching
• Kernel bypass — DPDK, RDMA, onload/ef_vi for sub-microsecond network I/O
• Memory discipline — pool allocators, slab allocation, zero dynamic allocation in hot path, NUMA-aware design
• Performance engineering — perf, Valgrind, flamegraphs, hardware PMU counters, L1/L2/LLC miss analysis

Acceleration of Parallel SAT Solver for Cryptanalysis of Hash Functions
Co-author · NSU Cryptography Summer School-Conference 2025 · pp. 132-142

Up to 41% runtime reduction on multi-threaded configurations via low-level algorithmic optimization.

WorldSkills — 2nd place, Neural Interface Design (2026)

English — fluent. Open to relocation globally.