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@3l1 3l1 commented Oct 27, 2025

Summary:
This diff fixes critical runtime bugs in U55 INT16 table operations (rsqrt, sigmoid, tanh)

WARNING: This diff goes with the Regor diff D85535937 and is only split because it maps to a separate OSS github repo (the Arm Regor git repo)

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Differential Revision: D85312140

cc @freddan80 @per @zingo @oscarandersson8218 @digantdesai

@3l1 3l1 requested a review from digantdesai as a code owner October 27, 2025 03:26
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pytorch-bot bot commented Oct 27, 2025

🔗 Helpful Links

🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/15390

Note: Links to docs will display an error until the docs builds have been completed.

❗ 2 Active SEVs

There are 2 currently active SEVs. If your PR is affected, please view them below:

❌ 17 New Failures, 1 Cancelled Job, 11 Unrelated Failures

As of commit ae665fa with merge base 4c58010 (image):

NEW FAILURES - The following jobs have failed:

CANCELLED JOB - The following job was cancelled. Please retry:

FLAKY - The following jobs failed but were likely due to flakiness present on trunk:

BROKEN TRUNK - The following jobs failed but were present on the merge base:

👉 Rebase onto the `viable/strict` branch to avoid these failures

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@meta-cla meta-cla bot added the CLA Signed This label is managed by the Facebook bot. Authors need to sign the CLA before a PR can be reviewed. label Oct 27, 2025
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meta-codesync bot commented Oct 27, 2025

@3l1 has exported this pull request. If you are a Meta employee, you can view the originating Diff in D85312140.

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3l1 commented Oct 27, 2025

@pytorchbot label "release notes: none"

@pytorch-bot pytorch-bot bot added the release notes: none Do not include this in the release notes label Oct 27, 2025
3l1 added a commit that referenced this pull request Oct 27, 2025
Summary:

This diff fixes critical runtime bugs in U55 INT16 table operations (rsqrt, sigmoid, tanh)

**WARNING: This diff goes with the Regor diff D85535937 and is only split because it maps to a separate OSS github repo (the Arm  Regor git repo)**

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Differential Revision: D85312140
@3l1 3l1 force-pushed the export-D85312140 branch from 76c7ac7 to 2818744 Compare October 27, 2025 05:56
@3l1 3l1 changed the title Fix U55 int16 table generation (rsqrt, sigmoid, tanh) Fix U55 int16 table generation Oct 27, 2025
facebook-github-bot pushed a commit that referenced this pull request Oct 27, 2025
Summary:

This diff fixes critical runtime bugs in U55 INT16 table operations (rsqrt, sigmoid, tanh)

**WARNING: This diff goes with the Regor diff D85535937 and is only split because it maps to a separate OSS github repo (the Arm  Regor git repo)**

bypass-github-export-checks
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Differential Revision: D85312140
@3l1 3l1 force-pushed the export-D85312140 branch from 5f1b2f2 to 69d9e88 Compare October 27, 2025 06:06
3l1 added a commit that referenced this pull request Oct 27, 2025
Summary:

This diff fixes critical runtime bugs in U55 INT16 table operations (rsqrt, sigmoid, tanh)

**WARNING: This diff goes with the Regor diff D85535937 and is only split because it maps to a separate OSS github repo (the Arm  Regor git repo)**

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Differential Revision: D85312140
@zingo zingo added the module: arm Issues related to arm backend label Oct 27, 2025
@zingo zingo changed the title Fix U55 int16 table generation Arm backedn: Fix U55 int16 table generation Oct 27, 2025
@zingo zingo added the partner: arm For backend delegation, kernels, demo, etc. from the 3rd-party partner, Arm label Oct 27, 2025
@3l1 3l1 requested review from SaoirseARM and gggekov October 27, 2025 13:34
facebook-github-bot pushed a commit that referenced this pull request Oct 27, 2025
Summary:

This diff fixes critical runtime bugs in U55 INT16 table operations (rsqrt, sigmoid, tanh)

**WARNING: This diff goes with the Regor diff D85535937 and is only split because it maps to a separate OSS github repo (the Arm  Regor git repo)**

bypass-github-export-checks
bypass-github-pytorch-ci-checks
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Differential Revision: D85312140
facebook-github-bot pushed a commit that referenced this pull request Oct 27, 2025
Summary:

This diff fixes critical runtime bugs in U55 INT16 table operations (rsqrt, sigmoid, tanh)

**WARNING: This diff goes with the Regor diff D85535937 and is only split because it maps to a separate OSS github repo (the Arm  Regor git repo)**

bypass-github-export-checks
bypass-github-pytorch-ci-checks
bypass-github-executorch-ci-checks

Differential Revision: D85312140
Summary:

This diff fixes critical runtime bugs in U55 INT16 table operations (rsqrt, sigmoid, tanh)

**WARNING: This diff goes with the Regor diff D85535937 and is only split because it maps to a separate OSS github repo (the Arm  Regor git repo)**

bypass-github-export-checks
bypass-github-pytorch-ci-checks
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Differential Revision: D85312140
@3l1 3l1 force-pushed the export-D85312140 branch from c7e7b03 to ae665fa Compare October 27, 2025 15:07
@3l1 3l1 changed the title Arm backedn: Fix U55 int16 table generation Arm backend: Fix U55 int16 table generation Oct 27, 2025
@3l1 3l1 requested a review from zingo October 27, 2025 15:26
@common.parametrize("test_data", test_data_suite)
@common.parametrize("test_data", test_data_suite_no_rand_4d)
@common.XfailIfNoCorstone300
@pytest.mark.xfail(
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todo: restore xfails unti regor oss is in sync

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3l1 commented Oct 28, 2025

I am told by Arm that they have an alternate, TOSA compliant, solution in Regor https://gitlab.arm.com/artificial-intelligence/ethos-u/ethos-u-vela/-/commit/5e8dd39861595e62287340802ab37812bda3d369 & https://gitlab.arm.com/artificial-intelligence/ethos-u/ethos-u-vela/-/commit/90e7cff2426c36876a2d2115b84844ecb39040ef

let's wait until this makes it to the Executorch repo before deciding to land this PR or not

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@zingo zingo marked this pull request as draft October 30, 2025 07:49
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zingo commented Oct 30, 2025

Move this to "draft" while waiting on Vela, just did it for slightly easier overview on GitHub, feel free to disagree and put it back of you want it as non draft if work both ways for me :) .

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