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    3 repositories

    • taxi

      Public
      AXI, AXI stream, Ethernet, and PCIe components in System Verilog
      SystemVerilog
      •
      CERN Open Hardware Licence Version 2 - Strongly Reciprocal
      •136•881•22•3•Updated Aug 12, 2026Aug 12, 2026

    • dpdk

      Public
      Data Plane Development Kit
      C
      •1.5k•2•0•0•Updated Mar 24, 2026Mar 24, 2026

    • corundum

      Public
      Open source FPGA-based NIC and platform for in-network compute
      Verilog
      •
      Other
      •548•17•0•0•Updated May 22, 2024May 22, 2024
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