Add Catalyst N1 & N2 neuromorphic processors to hardware guide

[Mr-wabbit]

Summary

This PR adds a new hardware entry for the Catalyst N1 and N2 neuromorphic processors to the hardware guide.

Catalyst N1 and N2 are open-architecture digital neuromorphic processors deployed on Xilinx VU47P FPGAs (AWS F2 instances), designed by Catalyst Neuromorphic Ltd. Key specifications:

• 128 neurosynaptic cores, 131,072 CUBA LIF neurons, 134M max synapses (CSR sparse encoding)
• On-chip learning: STDP, three-factor learning rules, per-group plasticity
• N1: Full Intel Loihi 1 feature parity
• N2: Full Loihi 2 feature parity — programmable neuron microcode, 5 neuron models (CUBA, Izhikevich, adLIF, Sigma-Delta, R&F), graded spikes, convolutional synapses
• Published benchmarks: SHD 90.7%, N-MNIST 99.2%, SSC 72.1%, Google Speech Commands 88.0%
• Published papers: N1 (Zenodo), N2 (Zenodo)
• Cloud API available at api.catalyst-neuromorphic.com

The entry follows the neuromorphic-hardware archetype format and includes all required front matter fields.

Checklist

• Follows neuromorphic-hardware archetype structure
• Front matter includes all product specification fields
• Includes overview, architecture, software, benchmarks, publications, and availability sections
• Org logo image included
• Higher-resolution product/chip image (can provide if requested)

Notes

The main image currently uses the GitHub org avatar. I'm happy to provide a higher-resolution hardware diagram or chip image if the maintainers prefer a different visual.

[neural-loop]

Hi @eljoserass Could you review this please?

[aMarcireau]

This looks very interesting and I think that this has its place on the ONM website.

However, our hardware category only lists ASICs for now. Catalysts' N1 and N2 architectures are almost software-like in my opinion (I am tempted to compare them to GPU compute shaders, except that they target cloud FPGAs) and might be a better fit for our software list (or perhaps in a brand-new "FPGA" category?).

As a side note, were the articles listed in "published papers" peer-reviewed and published in scientific journals, or are they white papers from the company? Could you precise your role or relationship with the company Catalyst and the University of Aberdeen?

[Mr-wabbit]

Thanks for the review, and fair point on all three.

On categorization: Catalyst is RTL (Verilog), not a software simulator, but you're right that there's no fabricated chip. I'm open to whatever fits best — a new FPGA category, the software list, or staying in hardware with a clear "FPGA implementation" label. Happy to restructure the entry to match whatever you decide.

On the publications: they're preprints on Zenodo, not peer-reviewed. I've updated the listing to make that clear.

On disclosure: I'm Henry Shulayev Barnes, founder of Catalyst Neuromorphic and a student at the University of Aberdeen. I should have stated that upfront, apologies.

I've pushed an update that also fixes several errors in the original submission: corrected the licensing to Apache 2.0 (was incorrectly listed as BSL 1.1), added N3, updated benchmark numbers, removed the cloud API references, and trimmed the entry to match the density of the other hardware listings.