Add LLVM-targeting compiler backend and SIMD matrix support

[cmontella]

Motivation

• Provide a new compiler pipeline that parses Mech source, runs it through the existing bytecode interpreter, and lowers bytecode to LLVM IR text for downstream codegen or inspection.
• Introduce a SIMD-friendly dense f32 matrix type to enable AVX-accelerated kernels for matrix operations when the target supports it.
• Expose the compiler behind a compiler feature so the compiler surface is opt-in for consumers.

Description

• Add src/compiler/mod.rs which implements LlvmCompiler, CompilerConfig, OptLevel, CompiledModule, and CompilerError, and a simple lowering from ParsedProgram bytecode to LLVM IR text via lower_bytecode_to_llvm_ir.
• Integrate with the existing Mech pipeline by invoking mech_interpreter::Interpreter to interpret and compile a Program into bytecode and ParsedProgram before lowering.
• Add src/compiler/simd.rs which defines MatrixF32 and an add implementation that dispatches to an AVX-optimized add_avx on x86_64 when avx is detected, with a portable fallback.
• Update src/lib.rs to conditionally expose the compiler module with #[cfg(feature = "compiler")] and add unit tests for the compiler pipeline and matrix addition.

Testing

• Ran the crate unit tests for the new compiler feature with cargo test --features compiler, which executed compile_source_uses_mech_pipeline and matrix_add_works and reported success.
• Verified the new unit tests assert non-empty bytecode and LLVM IR patterns and correct matrix addition behavior, and they passed.

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Codex Task