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1 change: 1 addition & 0 deletions tests/test_config.py
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
TEST_FREQUENCY_HZ = 1000000
5 changes: 3 additions & 2 deletions tests/test_spi.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
SDI -> SQ1 and LA4
SPI.CS -> LA3
"""

from test_config import TEST_FREQUENCY_HZ
import pytest
import re
from numpy import ndarray
Expand All @@ -30,7 +30,8 @@
CS = "LA3"
SPIMaster._primary_prescaler = PPRE = 0
SPIMaster._secondary_prescaler = SPRE = 0
PWM_FERQUENCY = SPIMaster._frequency * 2 / 3
# Hardcoded to 1MHz for testing
PWM_FERQUENCY = TEST_FREQUENCY_HZ * 2 / 3
MICROSECONDS = 1e-6
RELTOL = 0.05
# Number of expected logic level changes.
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4 changes: 3 additions & 1 deletion tests/test_uart.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@
"""

import pytest
from test_config import TEST_FREQUENCY_HZ

from pslab.bus.uart import UART
from pslab.instrument.logic_analyzer import LogicAnalyzer
Expand All @@ -16,7 +17,8 @@
WRITE_DATA = 0x55
TXD2 = "LA1"
RXD2 = "SQ1"
PWM_FERQUENCY = UART._baudrate // 2
# Hardcoded to 1MHz for testing
PWM_FREQUENCY = TEST_FREQUENCY_HZ // 2
MICROSECONDS = 1e-6
RELTOL = 0.05
# Number of expected logic level changes.
Expand Down