build: io: add multibit/bus variants of SDR and DDR

[maass-hamburg]

add bus variants of SDR and DDR, which
support more than one pin.

[enjoy-digital]

Thanks @maass-hamburg for the different PRs! Would you mind explaining the use-cases in the PR to be able to review the PR having the use-cases in mind?

[maass-hamburg]

@enjoy-digital
for example in the sdr phy in litespi this:

            for i in range(len(pads.dq)):
                self.specials += SDRTristate(
                    io = pads.dq[i],
                    o  = dq_o[i],
                    oe = dq_oe[i],
                    i  = dq_i[i],
                )

could be replaced with:

            self.specials += SDRTristateBus(
                    io = pads.dq,
                    o  = dq_o,
                    oe = dq_oe,
                    i  = dq_i,
                )

[maass-hamburg]

@enjoy-digital IMO the prefered way to go instead of this would be to have the regular SDR/DDR variants support longer lengths than 1, just like the migen Tristate, but that would need changes to all vendor-specific implementations. But I also don't know, if that's the way litex should go.

[enjoy-digital]

@maass-hamburg: That's indeed what I also tought when having a first look at the PR. If it's too much work to do it for all vendor initially, we could also just have assert in implementations to only build for the supported cases.

[maass-hamburg]

@enjoy-digital I implemented this now also for all of the other vendors, but in a generic way, which should function, but might not be the most efficient way for that platform.

[maass-hamburg]

@enjoy-digital rebased it, due to conflicts

[maass-hamburg]

@enjoy-digital please take a look, would be nice to get this merged soon.

[enjoy-digital]

@maass-hamburg: Thanks, I try to do this soon.

[enjoy-digital]

Thanks @maass-hamburg, this looks fine. I think we should be able to simplify things and just use for the following constructs: i[j] instead of i[j] if len(i) > 1 else i and same for all Input/Output/InOut?

[maass-hamburg]

@enjoy-digital I changed it.

[enjoy-digital]

@maass-hamburg: Great, thanks. This looks fine. I'll just try to build some design with it and if OK, will merge.

[enjoy-digital]

@maass-hamburg, this is merged. I had to do a few changes on top to avoid verilog slicing issues: 0bfaf39, e71e404 and 279b758.

[maass-hamburg]

@enjoy-digital Thanks, I also started a PR regarding slicing in migen, that might help and reduce useless slices: m-labs/migen#299