Add spike RISC-V simulator support#184
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widlarizer wants to merge 4 commits intoembench:masterfrom
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Resulting time parsing isn't implemented yet due to riscv-software-src/riscv-isa-sim#1493 |
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That implemented cycle count parsing. The ISA is hard coded to RV32GC and letting that be configurable is another open question |
added 2 commits
November 1, 2023 15:15
…et code, fail on non-zero benchmark ret code
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As unhelpful it may be for performance testing, spike is a valid target for evaluating compilers on code size while ensuring the benchmarks are still functional. This directory has been glued together from various fragments of community code with original licenses ensured to be GPL compatible and copyright notices modified with SPDX tags added. Some open questions: