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Merge pull request #1302 from diffblue/verilog_zero_extend_exprt
Verilog: use `zero_extend_exprt`
2 parents f5c9cb2 + 653b73b commit edcbc8d

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6 files changed

+55
-34
lines changed

6 files changed

+55
-34
lines changed
Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
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CORE
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verilog6.sv
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--smv-word-level
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^CTLSPEC 0ud8_1 \+ 0ub6_000000 :: -0sd2_1 = 0ud8_4$
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^EXIT=0$
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^SIGNAL=0$
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--
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@@ -0,0 +1,6 @@
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module main(input clk, input in);
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// The RHS of the addition will be zero-extended
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initial p1: assert property (8'b1 + 2'sb11 == 8'b100);
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endmodule

src/smvlang/expr2smv.cpp

Lines changed: 36 additions & 0 deletions
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@@ -350,6 +350,25 @@ expr2smvt::resultt expr2smvt::convert_typecast(const typecast_exprt &expr)
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/*******************************************************************\
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Function: expr2smvt::convert_zero_extend
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Inputs:
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Outputs:
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Purpose:
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\*******************************************************************/
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expr2smvt::resultt expr2smvt::convert_zero_extend(const zero_extend_exprt &expr)
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{
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// Both "extend" and "resize" do sign extension.
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// Hence, use lowering.
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return convert_rec(expr.lower());
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}
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/*******************************************************************\
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Function: expr2smvt::convert_rtctl
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Inputs:
@@ -662,6 +681,20 @@ expr2smvt::resultt expr2smvt::convert_constant(const constant_exprt &src)
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dest = minus + std::string("0") + sign_specifier + 'd' +
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std::to_string(word_width) + '_' + integer2string(value_abs);
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}
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else if(type.id() == ID_bv)
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{
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auto &bv_type = to_bv_type(type);
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auto width = bv_type.width();
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auto &src_value = src.get_value();
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dest = std::string("0ub");
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dest += std::to_string(width);
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dest += '_';
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for(std::size_t i = 0; i < width; i++)
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{
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bool bit = get_bvrep_bit(src_value, width, width - i - 1);
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dest += bit ? '1' : '0';
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}
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}
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else
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return convert_norep(src);
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@@ -912,6 +945,9 @@ expr2smvt::resultt expr2smvt::convert_rec(const exprt &src)
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return convert_typecast(to_typecast_expr(src));
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}
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else if(src.id() == ID_zero_extend)
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return convert_zero_extend(to_zero_extend_expr(src));
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else // no SMV language expression for internal representation
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return convert_norep(src);
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}

src/smvlang/expr2smv_class.h

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@@ -131,6 +131,8 @@ class expr2smvt
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resultt convert_typecast(const typecast_exprt &);
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resultt convert_zero_extend(const zero_extend_exprt &);
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resultt convert_norep(const exprt &);
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};
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src/verilog/expr2verilog.cpp

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Original file line numberDiff line numberDiff line change
@@ -2007,6 +2007,9 @@ expr2verilogt::resultt expr2verilogt::convert_rec(const exprt &src)
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return convert_function(src.id_string(), src);
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}
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else if(src.id() == ID_zero_extend)
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return convert_rec(to_zero_extend_expr(src).op());
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// no VERILOG language expression for internal representation
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return convert_norep(src);
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}

src/verilog/verilog_typecheck_expr.cpp

Lines changed: 1 addition & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -302,39 +302,6 @@ void verilog_typecheck_exprt::assignment_conversion(
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/*******************************************************************\
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Function: zero_extend
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Inputs:
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Outputs:
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Purpose:
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\*******************************************************************/
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static exprt zero_extend(const exprt &expr, const typet &type)
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{
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auto old_width = expr.type().id() == ID_bool ? 1
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: expr.type().id() == ID_integer
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? 32
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: to_bitvector_type(expr.type()).get_width();
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// first make unsigned
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typet tmp_type;
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if(type.id() == ID_unsignedbv)
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tmp_type = unsignedbv_typet{old_width};
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else if(type.id() == ID_verilog_unsignedbv)
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tmp_type = verilog_unsignedbv_typet{old_width};
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else
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PRECONDITION(false);
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return typecast_exprt::conditional_cast(
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typecast_exprt::conditional_cast(expr, tmp_type), type);
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}
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/*******************************************************************\
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Function: verilog_typecheck_exprt::downwards_type_progatation
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Inputs:
@@ -411,7 +378,7 @@ void verilog_typecheck_exprt::downwards_type_propagation(
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// "If the operand shall be extended, then it shall be sign-extended only
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// if the propagated type is signed."
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// A typecast from signed to a larger unsigned would sign extend.
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expr = zero_extend(expr, type);
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expr = zero_extend_exprt{expr, type};
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}
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else
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{

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