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lines changed Original file line number Diff line number Diff line change 1+ KNOWNBUG
2+ implies3.smv
3+ --buechi --bound 5
4+ ^EXIT=0$
5+ ^SIGNAL=0$
6+ --
7+ ^warning: ignoring
8+ --
9+ This fails since Spot uses a different atom numbering than we do.
Original file line number Diff line number Diff line change 1+ MODULE main
2+
3+ VAR x : 0..3;
4+
5+ ASSIGN
6+ init(x) := 1;
7+
8+ next(x) :=
9+ case
10+ x=3 : 3;
11+ TRUE: x+1;
12+ esac;
13+
14+ LTLSPEC ! (F x = 1 -> F x = 0) -- should pass
Original file line number Diff line number Diff line change 1+ KNOWNBUG
2+ ../../verilog/SVA/sequence_and1.sv
3+ --buechi --bdd
4+ ^\[main\.p0\] main\.x == 0 and main\.x == 1: REFUTED$
5+ ^\[main\.p1\] strong\(main\.x == 0 and main\.x == 1\): REFUTED$
6+ ^\[main\.p2\] main\.x == 0 and \(nexttime main\.x == 1\): PROVED$
7+ ^\[main\.p3\] \(nexttime main\.x == 1\) and main\.x == 0: PROVED$
8+ ^\[main\.p4\] \(main\.x == 0 and main\.x != 10\) |=> main\.x == 1: PROVED$
9+ ^EXIT=10$
10+ ^SIGNAL=0$
11+ --
12+ ^warning: ignoring
13+ --
14+ This fails since Spot's AP numbering differs.
Original file line number Diff line number Diff line change 1+ KNOWNBUG
2+ ../../verilog/SVA/sequence_and1.sv
3+ --buechi
4+ ^\[main\.p0\] main\.x == 0 and main\.x == 1: REFUTED$
5+ ^\[main\.p1\] strong\(main\.x == 0 and main\.x == 1\): REFUTED$
6+ ^\[main\.p2\] main\.x == 0 and \(nexttime main\.x == 1\): PROVED up to bound \d+$
7+ ^\[main\.p3\] \(nexttime main\.x == 1\) and main\.x == 0: PROVED up to bound \d+$
8+ ^\[main\.p4\] \(main\.x == 0 and main\.x != 10\) |=> main\.x == 1: PROVED up to bound \d+$
9+ ^EXIT=10$
10+ ^SIGNAL=0$
11+ --
12+ ^warning: ignoring
13+ --
14+ This fails since Spot's AP numbering differs.
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