SystemVerilog: KNOWNBUG test for cover disable iff

Author: kroening

regression/verilog/SVA/cover_sequence5.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+cover_sequence5.sv
+--bound 10
+^EXIT=10$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This gives the wrong answer.

regression/verilog/SVA/cover_sequence5.sv

@@ -0,0 +1,15 @@
+module main(input clk);
+
+  // count up
+  int x = 0;
+
+  always_ff @(posedge clk)
+    x++;
+
+  // never passes, owing to disable iff
+  p0: cover sequence (disable iff (1) 1);
+
+  // passes when reaching x=10
+  p1: cover sequence (disable iff (x<10) 1);
+
+endmodule