Verilog: Tests for explicit casts

This adds tests for size, signing and static casts.

Author: kroening

regression/verilog/expressions/signing_cast2.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+signing_cast2.sv
+--module main
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This is not yet implemented.

regression/verilog/expressions/signing_cast2.sv

@@ -0,0 +1,11 @@
+module main;
+
+  // four-valued signing cast
+  initial assert (signed'(4'b11xx) === 8'sb1111_11xx);
+  initial assert (signed'(4'bx000) === 8'sbxxxx_x000);
+
+  // four-valued signing cast
+  initial assert (unsigned'(4'sb11xx) === 8'b0000_11xx);
+  initial assert (unsigned'(4'sbx000) === 8'b0000_x000);
+
+endmodule

regression/verilog/expressions/signing_cast3.desc

@@ -0,0 +1,8 @@
+CORE
+signing_cast3.sv
+--module main
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--

regression/verilog/expressions/signing_cast3.sv

@@ -0,0 +1,9 @@
+module main;
+
+  // 1800-2017 6.24.1
+  // "the cast shall return the value that a variable of the casting type
+  // would hold after being assigned the expression."
+  // Hence, this is an assignment context with $bits width.
+  initial assert(signed'(1'b1 + 1'b1) == 0);
+
+endmodule

regression/verilog/expressions/size_cast2.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+size_cast2.sv
+--module main
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This is not yet implemented.

regression/verilog/expressions/size_cast2.sv

@@ -0,0 +1,11 @@
+module main;
+
+  // four-valued zero extension
+  initial assert (8'(4'b11xx) === 8'b0000_11xx);
+  initial assert (8'(4'bx000) === 8'b0000_x000);
+
+  // four-valued sign extension
+  initial assert (8'(4'sb11xx) === 8'sb1111_11xx);
+  initial assert (8'(4'sbx000) === 8'sbxxxx_x000);
+
+endmodule

regression/verilog/expressions/size_cast3.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+size_cast3.sv
+--module main
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This is not yet implemented.

regression/verilog/expressions/size_cast3.sv

@@ -0,0 +1,9 @@
+module main;
+
+  // 1800-2017 6.24.1
+  // "the cast shall return the value that a variable of the casting type
+  // would hold after being assigned the expression."
+  // Hence, this is an assignment context.
+  initial assert(8'(1'b1 + 1'b1) == 8'd2);
+
+endmodule

regression/verilog/expressions/static_cast3.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+static_cast3.sv
+--module main
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This is not yet implemented.

regression/verilog/expressions/static_cast3.sv

@@ -0,0 +1,11 @@
+module main;
+
+  typedef bit [7:0] eight_bits;
+
+  // 1800-2017 6.24.1
+  // "the cast shall return the value that a variable of the casting type
+  // would hold after being assigned the expression."
+  // Hence, this is an assignment context.
+  initial assert(eight_bits'(1'b1 + 1'b1) == 8'd2);
+
+endmodule