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Merge pull request #1320 from diffblue/error1-fix
Verilog: allow system function calls as module items
2 parents 44d8053 + 55e4da6 commit 953ccfa

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7 files changed

+19
-4
lines changed

7 files changed

+19
-4
lines changed
Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,8 @@
1-
KNOWNBUG
1+
CORE
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error1.v
33
--module main
4-
^EXIT=0$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
9-
This doesn't parse.

regression/verilog/system-functions/error1.v

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ module main;
22

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parameter P = 1;
44

5-
if(P!=1)
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if(P==1)
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$error("something is wrong");
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endmodule

src/verilog/parser.y

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1024,6 +1024,9 @@ module_or_generate_item:
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{ add_attributes($2, $1); $$=$2; }
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| attribute_instance_brace module_common_item
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{ add_attributes($2, $1); $$=$2; }
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// The next rule is not in 1800-2017, but is a vendor extension.
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| attribute_instance_brace system_tf_call ';'
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{ add_attributes($2, $1); $$ = $2; }
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;
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module_or_generate_item_declaration:

src/verilog/verilog_elaborate.cpp

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Original file line numberDiff line numberDiff line change
@@ -902,6 +902,10 @@ void verilog_typecheckt::collect_symbols(
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{
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collect_symbols(to_verilog_sequence_declaration(module_item));
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}
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else if(module_item.id() == ID_function_call)
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{
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// e.g., $error
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}
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else
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DATA_INVARIANT(false, "unexpected module item: " + module_item.id_string());
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}

src/verilog/verilog_interfaces.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -335,6 +335,9 @@ void verilog_typecheckt::interface_module_item(
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else if(module_item.id() == ID_verilog_sequence_declaration)
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{
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}
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else if(module_item.id() == ID_function_call)
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{
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}
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else
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{
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DATA_INVARIANT(false, "unexpected module item: " + module_item.id_string());

src/verilog/verilog_synthesis.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3424,6 +3424,9 @@ void verilog_synthesist::synth_module_item(
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else if(module_item.id() == ID_verilog_sequence_declaration)
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{
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}
3427+
else if(module_item.id() == ID_function_call)
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{
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}
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else
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{
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throw errort().with_location(module_item.source_location())

src/verilog/verilog_typecheck.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1972,6 +1972,9 @@ void verilog_typecheckt::convert_module_item(
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{
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convert_sequence_declaration(to_verilog_sequence_declaration(module_item));
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}
1975+
else if(module_item.id() == ID_function_call)
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{
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}
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else
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{
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throw errort().with_location(module_item.source_location())

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