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regression/verilog/system-functions Expand file tree Collapse file tree 7 files changed +19
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lines changed Original file line number Diff line number Diff line change 1- KNOWNBUG
1+ CORE
22error1.v
33--module main
4- ^EXIT=0 $
4+ ^EXIT=10 $
55^SIGNAL=0$
66--
77^warning: ignoring
88--
9- This doesn't parse.
Original file line number Diff line number Diff line change @@ -2,7 +2,7 @@ module main;
22
33 parameter P = 1 ;
44
5- if (P! =1 )
5+ if (P= =1 )
66 $error("something is wrong" );
77
88endmodule
Original file line number Diff line number Diff line change @@ -1024,6 +1024,9 @@ module_or_generate_item:
10241024 { add_attributes ($2 , $1 ); $$=$2 ; }
10251025 | attribute_instance_brace module_common_item
10261026 { add_attributes ($2 , $1 ); $$=$2 ; }
1027+ // The next rule is not in 1800-2017, but is a vendor extension.
1028+ | attribute_instance_brace system_tf_call ' ;'
1029+ { add_attributes ($2 , $1 ); $$ = $2 ; }
10271030 ;
10281031
10291032module_or_generate_item_declaration:
Original file line number Diff line number Diff line change @@ -902,6 +902,10 @@ void verilog_typecheckt::collect_symbols(
902902 {
903903 collect_symbols (to_verilog_sequence_declaration (module_item));
904904 }
905+ else if (module_item.id () == ID_function_call)
906+ {
907+ // e.g., $error
908+ }
905909 else
906910 DATA_INVARIANT (false , " unexpected module item: " + module_item.id_string ());
907911}
Original file line number Diff line number Diff line change @@ -335,6 +335,9 @@ void verilog_typecheckt::interface_module_item(
335335 else if (module_item.id () == ID_verilog_sequence_declaration)
336336 {
337337 }
338+ else if (module_item.id () == ID_function_call)
339+ {
340+ }
338341 else
339342 {
340343 DATA_INVARIANT (false , " unexpected module item: " + module_item.id_string ());
Original file line number Diff line number Diff line change @@ -3424,6 +3424,9 @@ void verilog_synthesist::synth_module_item(
34243424 else if (module_item.id () == ID_verilog_sequence_declaration)
34253425 {
34263426 }
3427+ else if (module_item.id () == ID_function_call)
3428+ {
3429+ }
34273430 else
34283431 {
34293432 throw errort ().with_location (module_item.source_location ())
Original file line number Diff line number Diff line change @@ -1972,6 +1972,9 @@ void verilog_typecheckt::convert_module_item(
19721972 {
19731973 convert_sequence_declaration (to_verilog_sequence_declaration (module_item));
19741974 }
1975+ else if (module_item.id () == ID_function_call)
1976+ {
1977+ }
19751978 else
19761979 {
19771980 throw errort ().with_location (module_item.source_location ())
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