Merge pull request #1324 from diffblue/synth-assignment-rec-signature

Verilog: modernise signature of `verilog_synthesist::assignment_rec`

Author: tautschnig

src/verilog/verilog_synthesis.cpp

@@ -649,8 +649,7 @@ void verilog_synthesist::assignment_rec(
   {
     assert(value_map!=NULL);
 
-    exprt new_rhs(rhs), new_value;
-    assignment_rec(lhs, new_rhs, new_value); // start of recursion
+    auto new_value = assignment_rec(lhs, rhs); // start of recursion
 
     if(new_value.is_not_nil())
     {
@@ -683,15 +682,11 @@ Function: verilog_synthesist::assignment_rec
 
 \*******************************************************************/
 
-void verilog_synthesist::assignment_rec(
-  const exprt &lhs,
-  exprt &rhs,
-  exprt &new_value)
+exprt verilog_synthesist::assignment_rec(const exprt &lhs, const exprt &rhs)
 {
   if(lhs.id()==ID_symbol)
   {
-    new_value.swap(rhs);
-    rhs.clear();
+    return rhs;
   }
   else if(lhs.id()==ID_index ||
           lhs.id()==ID_extractbit)
@@ -718,7 +713,7 @@ void verilog_synthesist::assignment_rec(
     new_rhs.where() = synth_expr(new_rhs.where(), symbol_statet::CURRENT);
 
     // do the value
-    assignment_rec(lhs_array, new_rhs, new_value); // recursive call
+    return assignment_rec(lhs_array, new_rhs); // recursive call
   }
   else if(lhs.id() == ID_verilog_non_indexed_part_select)
   {
@@ -749,8 +744,7 @@ void verilog_synthesist::assignment_rec(
     // redundant?
     if(from == 0 && to == get_width(lhs_src.type()) - 1)
     {
-      assignment_rec(lhs_src, rhs, new_value); // recursive call
-      return;
+      return assignment_rec(lhs_src, rhs); // recursive call
     }
 
     // turn
@@ -791,7 +785,7 @@ void verilog_synthesist::assignment_rec(
       new_rhs.add_to_operands(std::move(rhs_extractbit));
 
       // do the value
-      assignment_rec(lhs_src, new_rhs, new_value); // recursive call
+      exprt new_value = assignment_rec(lhs_src, new_rhs); // recursive call
 
       if(last_value.is_nil())
         last_value.swap(new_value);
@@ -809,7 +803,7 @@ void verilog_synthesist::assignment_rec(
       }
     }
 
-    new_value.swap(last_value);
+    return last_value;
   }
   else if(
     lhs.id() == ID_verilog_indexed_part_select_plus ||
@@ -878,7 +872,7 @@ void verilog_synthesist::assignment_rec(
       new_rhs.add_to_operands(std::move(rhs_extractbit));
 
       // do the value
-      assignment_rec(lhs_src, new_rhs, new_value); // recursive call
+      exprt new_value = assignment_rec(lhs_src, new_rhs); // recursive call
 
       if(last_value.is_nil())
         last_value.swap(new_value);
@@ -896,7 +890,7 @@ void verilog_synthesist::assignment_rec(
       }
     }
 
-    new_value.swap(last_value);
+    return last_value;
   }
   else if(lhs.id() == ID_member)
   {
@@ -918,7 +912,7 @@ void verilog_synthesist::assignment_rec(
         synth_compound, member_designatort{component_name}, rhs};
 
       // recursive call
-      assignment_rec(lhs_compound, new_rhs, new_value); // recursive call
+      return assignment_rec(lhs_compound, new_rhs); // recursive call
     }
     else
     {
@@ -929,24 +923,6 @@ void verilog_synthesist::assignment_rec(
   {
     throw errort() << "unexpected lhs: " << lhs.id();
   }
-
-  #if 0
-  // do "with" merging
-
-  if(new_value.id()==ID_with &&
-     new_value.op0().id()==ID_with)
-  {
-    exprt tmp;
-
-    tmp.swap(new_value.op0());
-
-    tmp.reserve_operands(tmp.operands().size()+2);
-    tmp.add_to_operands(std::move(new_value.op1()));
-    tmp.add_to_operands(std::move(new_value.op2()));
-
-    new_value.swap(tmp);
-  }
-  #endif
 }
 
 /*******************************************************************\

src/verilog/verilog_synthesis_class.h

@@ -222,10 +222,7 @@ class verilog_synthesist:
 
   void assignment_rec(const exprt &lhs, const exprt &rhs, bool blocking);
 
-  void assignment_rec(
-    const exprt &lhs,
-    exprt &rhs,
-    exprt &new_value);
+  exprt assignment_rec(const exprt &lhs, const exprt &rhs);
 
   const symbolt &assignment_symbol(const exprt &lhs);