Verilog: extend static_cast3 test

This adds signed cases to the static_cast3 test.

Author: kroening

regression/verilog/expressions/static_cast3.sv

@@ -1,11 +1,15 @@
 module main;
 
-  typedef bit [7:0] eight_bits;
+  typedef bit unsigned [7:0] unsigned_eight_bits;
+  typedef bit signed [7:0] signed_eight_bits;
 
   // 1800-2017 6.24.1
   // "the cast shall return the value that a variable of the casting type
   // would hold after being assigned the expression."
   // Hence, this is an assignment context.
-  initial assert(eight_bits'(1'b1 + 1'b1) == 8'd2);
+  initial assert(unsigned_eight_bits'(1'b1 + 1'b1) == 8'd2);
+  initial assert(unsigned_eight_bits'(1'sb1 + 1'sb1) == 8'b11111110);
+  initial assert(signed_eight_bits'(1'b1 + 1'b1) == 8'd2);
+  initial assert(signed_eight_bits'(1'sb1 + 1'sb1) == 8'sb11111110);
 
 endmodule