Merge pull request #1342 from diffblue/ports9-fix

Verilog: fix for port direction of output register ports

Author: tautschnig

CHANGELOG

@@ -1,6 +1,7 @@
 # EBMC 5.8
 
 * SystemVerilog: cover sequence
+* Verilog: semantic fix for output register ports
 
 # EBMC 5.7
 

regression/verilog/modules/ports9.desc

@@ -1,9 +1,8 @@
-KNOWNBUG
+CORE
 ports9.sv
 --bound 1
 ^EXIT=0$
 ^SIGNAL=0$
 --
 ^warning: ignoring
 --
-This gives the wrong answer.

src/verilog/verilog_interfaces.cpp

@@ -108,6 +108,10 @@ void verilog_typecheckt::check_module_ports(
       else
         direction = ID_inout;
     }
+    else if(direction == ID_output_register)
+    {
+      direction = ID_output;
+    }
 
     ports.emplace_back(identifier, port_symbol->type, direction);