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syntax-checks.yaml
1,964 workflow runs
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Verilog: fix for port direction of output register ports Syntactic checks #3164: Pull request #1342 synchronize by kroening
3m 15s ports9-fix
ports9-fix
3m 15s
SVA: add cover sequence Syntactic checks #3163: Pull request #1343 synchronize by kroening
3m 1s cover_sequence_statement
cover_sequence_statement
3m 1s
SVA: add cover sequence Syntactic checks #3162: Pull request #1343 synchronize by kroening
1m 39s cover_sequence_statement
cover_sequence_statement
1m 39s
SystemVerilog: KNOWNBUG test for cover disable iff Syntactic checks #3161: Pull request #1344 opened by kroening
1m 38s cover_sequence5
cover_sequence5
1m 38s
SVA: add cover sequence Syntactic checks #3160: Pull request #1343 synchronize by kroening
2m 58s cover_sequence_statement
cover_sequence_statement
2m 58s
SVA: add cover sequence Syntactic checks #3159: Pull request #1343 opened by kroening
2m 48s cover_sequence_statement
cover_sequence_statement
2m 48s
Verilog: fix for port direction of output register ports Syntactic checks #3158: Pull request #1342 opened by kroening
2m 24s ports9-fix
ports9-fix
2m 24s
KNOWNBUG test for module port constraints Syntactic checks #3157: Pull request #1341 synchronize by kroening
2m 38s ports9
ports9
2m 38s
KNOWNBUG test for module port constraints Syntactic checks #3156: Pull request #1341 opened by kroening
1m 38s ports9
ports9
1m 38s
Verilog: explicit casts are assignments Syntactic checks #3155: Pull request #1340 synchronize by kroening
1m 39s verilog-size-cast
verilog-size-cast
1m 39s
Verilog: explicit casts are assignments Syntactic checks #3154: Pull request #1340 synchronize by kroening
1m 39s verilog-size-cast
verilog-size-cast
1m 39s
Verilog: explicit casts are assignments Syntactic checks #3153: Pull request #1340 synchronize by kroening
2m 48s verilog-size-cast
verilog-size-cast
2m 48s
Verilog: explicit casts are assignments Syntactic checks #3152: Pull request #1340 synchronize by kroening
3m 6s verilog-size-cast
verilog-size-cast
3m 6s
Verilog: Tests for signing and size casts Syntactic checks #3151: Pull request #1339 synchronize by kroening
2m 43s size_cast-tests
size_cast-tests
2m 43s
Verilog: explicit casts are assignments Syntactic checks #3150: Pull request #1340 synchronize by kroening
2m 41s verilog-size-cast
verilog-size-cast
2m 41s
Verilog: explicit casts are assignments Syntactic checks #3149: Pull request #1340 opened by kroening
1m 37s verilog-size-cast
verilog-size-cast
1m 37s
Verilog: Tests for signing and size casts Syntactic checks #3148: Pull request #1339 synchronize by kroening
1m 43s size_cast-tests
size_cast-tests
1m 43s
Verilog: Tests for signing and size casts Syntactic checks #3147: Pull request #1339 opened by kroening
3m 11s size_cast-tests
size_cast-tests
3m 11s
Verilog: lowering for four-valued zero-extend Syntactic checks #3146: Pull request #796 synchronize by kroening
3m 3s zero-extend
zero-extend
3m 3s
Generate VCD file for each cover statement Syntactic checks #3145: Pull request #1296 synchronize by ShashankVM
7m 13s ShashankVM:vcd_for_all_cover
ShashankVM:vcd_for_all_cover
7m 13s
Verilog: test for signing casts Syntactic checks #3143: Pull request #1336 opened by kroening
2m 36s signing_cast1-ext
signing_cast1-ext
2m 36s
KNOWNBUG for unsized integer literals Syntactic checks #3142: Pull request #1335 synchronize by kroening
3m 1s integer_literals3
integer_literals3
3m 1s
KNOWNBUG for unsized integer literals Syntactic checks #3141: Pull request #1335 opened by kroening
1m 38s integer_literals3
integer_literals3
1m 38s
Verilog: tests for unsigned integer literals Syntactic checks #3140: Pull request #1334 opened by kroening
3m 4s integer_literals2
integer_literals2
3m 4s
Verilog: default aval/bval lowering Syntactic checks #3139: Pull request #668 synchronize by kroening
2m 40s default_aval_bval_encoding
default_aval_bval_encoding
2m 40s
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