[ENG-1975] Fix clock rise/fall edge on 0 for non_seq timing types#53
[ENG-1975] Fix clock rise/fall edge on 0 for non_seq timing types#53
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Greptile SummaryThis PR fixes incorrect cycle accounting for
Confidence Score: 5/5Safe to merge — the one-line additions are narrowly scoped, follow the exact same pattern as the surrounding setup/hold roles, and are backed by a new regression test that exercises the corrected code path. The change touches only two helper functions in CycleAccting.cc, each receiving a single additional setAccting call that mirrors what every adjacent timing role already does. The new regression validates the fix end-to-end and the expected output is arithmetically consistent with the Liberty constraints. No existing behavior is altered. The new Liberty test library (test/non_seq_timing.lib) covers only rising-edge non-seq arcs; falling-edge variants mentioned in the PR description are not exercised by the test. Important Files Changed
Flowchart%%{init: {'theme': 'neutral'}}%%
flowchart TD
A["CycleAccting::findSrcCycles / findDefaultArrivalSrcDelays"] --> B["setDefaultSetupAccting(src, tgt, delay, req)"]
A --> C["setDefaultHoldAccting(src, tgt, delay, req)"]
B --> D["setSetupAccting(src, tgt, delay, req)"]
B --> E["setAccting(latchSetup)"]
B --> F["setAccting(dataCheckSetup)"]
D --> G["setAccting(setup)"]
D --> H["setAccting(outputSetup)"]
D --> I["setAccting(gatedClockSetup)"]
D --> J["setAccting(recovery)"]
D --> K["setAccting(nonSeqSetup) NEW"]
C --> L["setHoldAccting(src, tgt, delay, req)"]
C --> M["setAccting(dataCheckHold)"]
L --> N["setAccting(hold)"]
L --> O["setAccting(outputHold)"]
L --> P["setAccting(removal)"]
L --> Q["setAccting(latchHold)"]
L --> R["setAccting(nonSeqHold) NEW"]
Reviews (2): Last reviewed commit: "remove redundant" | Re-trigger Greptile |
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@greptile re-review |
non_seq_setup_rise
non_seq_setup_fall
non_seq_hold_rise
non_seq_hold_fall
not handled properly when populating data structure storing the clock edges to use when reporting timing checks.
leads to the release and capture clock being on the same edge, which is incorrect.
the change allows us to properly handle these timing types