PennyLaneAI · josephleekl · Aug 5, 2026 · Jul 20, 2026 · Jul 20, 2026 · Jul 20, 2026
diff --git a/doc/releases/changelog-dev.md b/doc/releases/changelog-dev.md
@@ -49,10 +49,15 @@
 * A `BufferizableOpInterface` implementation is added for the `Transport` dialect ops.
   [(#3064)](https://github.com/PennyLaneAI/catalyst/pull/3064)
 
-* A `lower-decode-to-transport` pass is added, which replaces each qecp.decode_esm_css with 
+* A `lower-decode-to-transport` pass is added, which replaces each qecp.decode_esm_css with
   a transport kick/collect round over its buffers.
   [(#3066)](https://github.com/PennyLaneAI/catalyst/pull/3066)
 
+* An X/Z syndrome decode can now be routed to its own decoder in a backline coprocessor.
+  `qecp.decode_esm_css` carries an optional `check_type` attribute recording which check family a
+  syndrome came from, which `lower-decode-to-transport` maps to a `decoder_id` on `transport.kick`.
+  [(#3092)](https://github.com/PennyLaneAI/catalyst/pull/3092)
+
 * A new remote/local executor infrastructure has been added to Catalyst, enabling qnode kernels to
   be dispatched to a separate executor process.
 

diff --git a/frontend/catalyst/python_interface/dialects/qecp.py b/frontend/catalyst/python_interface/dialects/qecp.py
@@ -32,6 +32,7 @@
     IndexType,
     IntegerAttr,
     IntegerType,
+    StringAttr,
     TensorType,
     UnitAttr,
     i1,
@@ -52,6 +53,7 @@
     AtLeast,
     BaseAttr,
     IRDLOperation,
+    ParsePropInAttrDict,
     TypeAttributeInvT,
     VarConstraint,
     base,
@@ -859,6 +861,10 @@ class DecodeEsmCssOp(IRDLOperation):
 
     err_idx = opt_result_def(TensorConstraint(element_type=IndexType(), rank=1))
 
+    check_type = opt_prop_def(StringAttr)
+
+    irdl_options = (ParsePropInAttrDict(),)
+
     def __init__(
         self,
         tanner_graph: TannerGraphSSAValue | Operation,

diff --git a/frontend/catalyst/python_interface/transforms/qecp/convert_qecl_to_qecp.py b/frontend/catalyst/python_interface/transforms/qecp/convert_qecl_to_qecp.py
@@ -49,6 +49,7 @@
     ArrayAttr,
     DenseArrayBase,
     IndexType,
+    StringAttr,
     SymbolRefAttr,
     TensorType,
     i1,
@@ -1322,6 +1323,7 @@ def _qec_cycle_css_pattern(
             esm=pack_mres_tensor_op.result,
             err_idx_type=TensorType(IndexType(), shape=(num_correctable_errors,)),
         )
+        decode_esm_op.properties["check_type"] = StringAttr(check_type.value.lower())
 
         # Apply correction(s)
         err_indices = cast(OpResult[TensorType[IndexType]], decode_esm_op.err_idx)

diff --git a/frontend/test/pytest/python_interface/transforms/qecp/test_xdsl_convert_qecl_to_qecp.py b/frontend/test/pytest/python_interface/transforms/qecp/test_xdsl_convert_qecl_to_qecp.py
@@ -531,7 +531,7 @@ def test_single_qec_cycle_Steane(self, run_filecheck, qecl_to_qecp_steane_pipeli
         // CHECK: qecp.dealloc_aux {{.*}} : !qecp.qubit<aux>
         // CHECK: qecp.dealloc_aux {{.*}} : !qecp.qubit<aux>
         // CHECK: [[esm:%.+]] = tensor.from_elements [[m0]], [[m1]], [[m2]] : tensor<3xi1>
-        // CHECK: [[idx_t:%.+]] = qecp.decode_esm_css([[tanner_x]] : !qecp.tanner_graph<24, 11, i32>) [[esm]] : tensor<3xi1> -> tensor<1xindex>
+        // CHECK: [[idx_t:%.+]] = qecp.decode_esm_css([[tanner_x]] : !qecp.tanner_graph<24, 11, i32>) [[esm]] {check_type = "x"} : tensor<3xi1> -> tensor<1xindex>
         // CHECK: [[lb:%.+]] = arith.constant 0 : index
         // CHECK: [[ub:%.+]] = arith.constant 1 : index
         // CHECK: [[st:%.+]] = arith.constant 1 : index
@@ -568,7 +568,7 @@ def test_single_qec_cycle_Steane(self, run_filecheck, qecl_to_qecp_steane_pipeli
         // CHECK: qecp.dealloc_aux {{.*}} : !qecp.qubit<aux>
         // CHECK: qecp.dealloc_aux {{.*}} : !qecp.qubit<aux>
         // CHECK: [[esm:%.+]] = tensor.from_elements [[m0]], [[m1]], [[m2]] : tensor<3xi1>
-        // CHECK: [[idx_t:%.+]] = qecp.decode_esm_css([[tanner_z]] : !qecp.tanner_graph<24, 11, i32>) [[esm]] : tensor<3xi1>  -> tensor<1xindex>
+        // CHECK: [[idx_t:%.+]] = qecp.decode_esm_css([[tanner_z]] : !qecp.tanner_graph<24, 11, i32>) [[esm]] {check_type = "z"} : tensor<3xi1>  -> tensor<1xindex>
         // CHECK: [[lb:%.+]] = arith.constant 0 : index
         // CHECK: [[ub:%.+]] = arith.constant 1 : index
         // CHECK: [[st:%.+]] = arith.constant 1 : index
@@ -1796,7 +1796,7 @@ def test_qec_cycle_shor(self, run_filecheck):
         // CHECK: qecp.dealloc_aux {{.*}} : !qecp.qubit<aux>
         // CHECK: qecp.dealloc_aux {{.*}} : !qecp.qubit<aux>
         // CHECK: [[esm:%.+]] = tensor.from_elements [[m0]], [[m1]] : tensor<2xi1>
-        // CHECK: [[idx_t:%.+]] = qecp.decode_esm_css([[tanner_x]] : !qecp.tanner_graph<24, 12, i32>) [[esm]] : tensor<2xi1> -> tensor<1xindex>
+        // CHECK: [[idx_t:%.+]] = qecp.decode_esm_css([[tanner_x]] : !qecp.tanner_graph<24, 12, i32>) [[esm]] {check_type = "x"} : tensor<2xi1> -> tensor<1xindex>
         // CHECK: [[lb:%.+]] = arith.constant 0 : index
         // CHECK: [[ub:%.+]] = arith.constant 1 : index
         // CHECK: [[st:%.+]] = arith.constant 1 : index
@@ -1842,7 +1842,7 @@ def test_qec_cycle_shor(self, run_filecheck):
         // CHECK: qecp.dealloc_aux {{.*}} : !qecp.qubit<aux>
         // CHECK: qecp.dealloc_aux {{.*}} : !qecp.qubit<aux>
         // CHECK: [[esm:%.+]] = tensor.from_elements [[m0]], [[m1]], [[m2]], [[m3]], [[m4]], [[m5]] : tensor<6xi1>
-        // CHECK: [[idx_t:%.+]] = qecp.decode_esm_css([[tanner_z]] : !qecp.tanner_graph<24, 16, i32>) [[esm]] : tensor<6xi1>  -> tensor<1xindex>
+        // CHECK: [[idx_t:%.+]] = qecp.decode_esm_css([[tanner_z]] : !qecp.tanner_graph<24, 16, i32>) [[esm]] {check_type = "z"} : tensor<6xi1>  -> tensor<1xindex>
         // CHECK: [[lb:%.+]] = arith.constant 0 : index
         // CHECK: [[ub:%.+]] = arith.constant 1 : index
         // CHECK: [[st:%.+]] = arith.constant 1 : index

diff --git a/mlir/include/QecPhysical/IR/QecPhysicalOps.td b/mlir/include/QecPhysical/IR/QecPhysicalOps.td
@@ -396,6 +396,10 @@ def DecodeEsmCssOp : QecPhysical_Op<"decode_esm_css"> {
         and Z checks. It is therefore up to the user of this operation to determine what type(s) of
         correction(s) to apply given the Tanner graph that was supplied.
 
+        The optional `check_type` attribute records which check family this syndrome came from
+        ("x" or "z"), so a consumer picking a decoder per parity-check matrix need not recover it by
+        tracing the Tanner graph operand.
+
         If no correctable error was detected, this operation returns an index value of -1.
 
         #### Example
@@ -422,7 +426,8 @@ def DecodeEsmCssOp : QecPhysical_Op<"decode_esm_css"> {
     let arguments = (ins
         AnyTypeOf<[1DTensorOf<[I1]>, MemRefRankOf<[I1], [1]>]>:$esm,
         TannerGraphType:$tanner_graph,
-        Optional<MemRefRankOf<[Index], [1]>>:$err_idx_in
+        Optional<MemRefRankOf<[Index], [1]>>:$err_idx_in,
+        OptionalAttr<StrAttr>:$check_type
     );
 
     let results = (outs

diff --git a/mlir/include/Transport/IR/TransportOps.td b/mlir/include/Transport/IR/TransportOps.td
@@ -130,7 +130,8 @@ def Transport_StartOp : Transport_Op<"start"> {
 def Transport_KickOp : Transport_Op<"kick"> {
     let summary = "Send a payload as one round's request (controller).";
     let arguments = (ins Transport_ControllerSession:$session, Transport_AnyBuffer:$payload,
-                         I32Attr:$work_item_idx);
+                         I32Attr:$work_item_idx,
+                         DefaultValuedOptionalAttr<I32Attr, "0">:$decoder_id);
     let assemblyFormat = "$session `,` $payload attr-dict `:` qualified(type($session)) `,` type($payload)";
 }
 

diff --git a/mlir/lib/QecPhysical/Transforms/BufferizableOpInterfaceImpl.cpp b/mlir/lib/QecPhysical/Transforms/BufferizableOpInterfaceImpl.cpp
@@ -124,7 +124,8 @@ struct DecodeEsmCssOpInterface
         Value errIdxBuffer = memref::AllocOp::create(rewriter, loc, errIdxMemRefType);
 
         DecodeEsmCssOp::create(rewriter, loc, TypeRange{}, esmToBufferOp.getResult(),
-                               decodeEsmCssOp.getTannerGraph(), errIdxBuffer);
+                               decodeEsmCssOp.getTannerGraph(), errIdxBuffer,
+                               decodeEsmCssOp.getCheckTypeAttr());
 
         bufferization::replaceOpWithBufferizedValues(rewriter, op, errIdxBuffer);
         return success();

diff --git a/mlir/lib/Transport/Transforms/LowerDecodeToTransport.cpp b/mlir/lib/Transport/Transforms/LowerDecodeToTransport.cpp
@@ -22,6 +22,7 @@
 
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "mlir/IR/Builders.h"
 #include "mlir/IR/BuiltinAttributes.h"
 #include "mlir/Pass/Pass.h"
@@ -68,11 +69,18 @@ struct LowerDecodeToTransportPass
         MLIRContext *ctx = &getContext();
         auto ctrlTy = SessionType::get(ctx, Role::Controller);
 
-        auto emitRound = [&](Operation *anchor, Value syndrome, Value correction, StringRef key) {
+        auto emitRound = [&](qecp::DecodeEsmCssOp anchor, Value syndrome, Value correction,
+                             StringRef key) {
             OpBuilder b(anchor);
             Value s = GetSessionOp::create(b, anchor->getLoc(), ctrlTy, b.getStringAttr(key))
                           .getSession();
-            KickOp::create(b, anchor->getLoc(), s, syndrome, b.getI32IntegerAttr(0));
+            const std::int32_t decoderSlot =
+                llvm::StringSwitch<std::int32_t>(anchor.getCheckType().value_or(""))
+                    .Case("x", 0)
+                    .Case("z", 1)
+                    .Default(0);
+            KickOp::create(b, anchor->getLoc(), s, syndrome, b.getI32IntegerAttr(0),
+                           b.getI32IntegerAttr(decoderSlot));
             CollectOp::create(b, anchor->getLoc(), TypeRange{}, ValueRange{s, correction});
             anchor->erase();
         };

diff --git a/mlir/lib/Transport/Transforms/TransportToLLVM.cpp b/mlir/lib/Transport/Transforms/TransportToLLVM.cpp
@@ -248,9 +248,10 @@ struct KickLowering : public OpConversionPattern<KickOp> {
         }
         auto [srcPtr, bytes] =
             memrefPtrAndBytes(rewriter, op.getLoc(), adaptor.getPayload(), memTy);
+        Value decoderId = constInt(rewriter, op.getLoc(), i32Ty(ctx), op.getDecoderId());
         emitCall(rewriter, op.getLoc(), mod, "__catalyst__transport__write_data_slot",
-                 {ptrTy(ctx), ptrTy(ctx), i64Ty(ctx)}, i32Ty(ctx),
-                 {adaptor.getSession(), srcPtr, bytes});
+                 {ptrTy(ctx), ptrTy(ctx), i64Ty(ctx), i32Ty(ctx)}, i32Ty(ctx),
+                 {adaptor.getSession(), srcPtr, bytes, decoderId});
         Value idx = constInt(rewriter, op.getLoc(), i32Ty(ctx), op.getWorkItemIdx());
         emitCall(rewriter, op.getLoc(), mod, "__catalyst__transport__kick",
                  {ptrTy(ctx), i32Ty(ctx)}, i32Ty(ctx), {adaptor.getSession(), idx});

diff --git a/mlir/test/Transport/ConvertTransportToLLVM.mlir b/mlir/test/Transport/ConvertTransportToLLVM.mlir
@@ -19,7 +19,7 @@
 // CHECK-DAG: llvm.func @__catalyst__transport__exchange_keys(!llvm.ptr) -> i32
 // CHECK-DAG: llvm.func @__catalyst__transport__establish_channel(!llvm.ptr, !llvm.ptr) -> i32
 // CHECK-DAG: llvm.func @__catalyst__transport__commit_work_item(!llvm.ptr, i32, i64, i64) -> i32
-// CHECK-DAG: llvm.func @__catalyst__transport__write_data_slot(!llvm.ptr, !llvm.ptr, i64) -> i32
+// CHECK-DAG: llvm.func @__catalyst__transport__write_data_slot(!llvm.ptr, !llvm.ptr, i64, i32) -> i32
 // CHECK-DAG: llvm.func @__catalyst__transport__kick(!llvm.ptr, i32) -> i32
 // CHECK-DAG: llvm.func @__catalyst__transport__collect(!llvm.ptr, !llvm.ptr, i64) -> i32
 // CHECK-DAG: llvm.func @__catalyst__transport__start(!llvm.ptr)

diff --git a/mlir/test/Transport/LowerDecodeToTransport.mlir b/mlir/test/Transport/LowerDecodeToTransport.mlir
@@ -96,3 +96,42 @@ module attributes {catalyst.backline = #transport.backline<transport = "net",
     return
   }
 }
+
+// -----
+
+// Check decode check_type mapping to decoder_id
+
+// CHECK-LABEL: func.func @qec_cycle_css
+// CHECK:         %[[SX:.*]] = transport.get_session {key = "cop0"} : !transport.session<controller>
+// CHECK:         transport.kick %[[SX]], %{{.*}} {work_item_idx = 0 : i32}
+// CHECK:         %[[SZ:.*]] = transport.get_session {key = "cop0"} : !transport.session<controller>
+// CHECK:         transport.kick %[[SZ]], %{{.*}} {decoder_id = 1 : i32, work_item_idx = 0 : i32}
+module attributes {catalyst.backline = #transport.backline<transport = "net",
+  controller = #transport.node<backend_lib = "x", config = "c">,
+  coprocessors = [#transport.node<backend_lib = "x", config = "c", name = "cop0", peer = "10.0.0.1", symbol = "decode">]>} {
+  func.func @qec_cycle_css(%tannerX: !qecp.tanner_graph<8, 6, i32>,
+                           %tannerZ: !qecp.tanner_graph<8, 6, i32>,
+                           %esmX: memref<?xi1>, %iX: memref<?xindex>,
+                           %esmZ: memref<?xi1>, %iZ: memref<?xindex>) {
+    qecp.decode_esm_css(%tannerX : !qecp.tanner_graph<8, 6, i32>) %esmX in (%iX : memref<?xindex>) {check_type = "x"} : memref<?xi1>
+    qecp.decode_esm_css(%tannerZ : !qecp.tanner_graph<8, 6, i32>) %esmZ in (%iZ : memref<?xindex>) {check_type = "z"} : memref<?xi1>
+    return
+  }
+}
+
+// -----
+
+// A decode that declares no check family takes decoder 0, so IR from before the attribute
+// existed lowers unchanged.
+
+// CHECK-LABEL: func.func @untagged
+// CHECK:         transport.kick %{{.*}} {work_item_idx = 0 : i32}
+// CHECK-NOT:     decoder_id
+module attributes {catalyst.backline = #transport.backline<transport = "net",
+  controller = #transport.node<backend_lib = "x", config = "c">,
+  coprocessors = [#transport.node<backend_lib = "x", config = "c", name = "cop0", peer = "10.0.0.1", symbol = "decode">]>} {
+  func.func @untagged(%tanner: !qecp.tanner_graph<8, 6, i32>, %esm: memref<?xi1>, %erridx: memref<?xindex>) {
+    qecp.decode_esm_css(%tanner : !qecp.tanner_graph<8, 6, i32>) %esm in (%erridx : memref<?xindex>) : memref<?xi1>
+    return
+  }
+}
diff --git a/runtime/include/Transport.hpp b/runtime/include/Transport.hpp
@@ -167,8 +167,9 @@ class ControllerSession : public TransportSession {
 
     // Copy `bytes` of payload into the current round's outbound slot, ready for kick().
     // Throws if `bytes` exceeds what the round was committed to carry, so an oversized
-    // payload will fail.
-    virtual void write_data_slot(const void *src, std::uint64_t bytes) = 0;
+    // payload will fail. `decoder_id` picks the coprocessor-side decoder for this round.
+    virtual void write_data_slot(const void *src, std::uint64_t bytes,
+                                 std::uint32_t decoder_id) = 0;
 
     // Current round's reply slot in the transport-owned reply ring.
     virtual void *reply_slot() { return nullptr; }
@@ -228,8 +229,9 @@ class CoprocessorSession : public TransportSession {
     /**
      * @brief Bind a per-message coprocessor function (CPU-style).
      *
-     * Call before start(). `fn` is invoked once per received message; `ctx` is
-     * passed back on every invocation and may be null.
+     * Call before start(). `fn` is invoked once per received message, receiving the
+     * message's decoder_id so it can dispatch internally; `ctx` is passed back on
+     * every invocation and may be null.
      */
     virtual void set_coprocessor_fn(CoprocessorFn /*fn*/, void * /*ctx*/) {
         throw std::logic_error(

diff --git a/runtime/include/TransportCAPI.h b/runtime/include/TransportCAPI.h
@@ -79,7 +79,7 @@ void *__catalyst__transport__data_slot(CatalystTransportSession *s);
 // Copy `bytes` into the round's outbound slot. Fails if `bytes` exceeds what
 // commit_work_item committed.
 int __catalyst__transport__write_data_slot(CatalystTransportSession *s, const void *src,
-                                           uint64_t bytes);
+                                           uint64_t bytes, uint32_t decoder_id);
 void *__catalyst__transport__reply_slot(CatalystTransportSession *s);
 int __catalyst__transport__kick(CatalystTransportSession *s, uint32_t work_item_idx);
 

diff --git a/runtime/lib/transport/TransportCAPI.cpp b/runtime/lib/transport/TransportCAPI.cpp
@@ -349,13 +349,13 @@ void *__catalyst__transport__data_slot(CatalystTransportSession *s) {
 }
 
 int __catalyst__transport__write_data_slot(CatalystTransportSession *s, const void *src,
-                                           std::uint64_t bytes) {
+                                           std::uint64_t bytes, std::uint32_t decoder_id) {
     auto *c = cast_to_controller(s);
     if (!c) {
         return CATALYST_TRANSPORT_ERR;
     }
     return guard([&] {
-        c->write_data_slot(src, bytes);
+        c->write_data_slot(src, bytes, decoder_id);
         return 0;
     });
 }

diff --git a/runtime/lib/transport/common/WireProtocol.hpp b/runtime/lib/transport/common/WireProtocol.hpp
@@ -38,11 +38,16 @@ inline constexpr std::uint64_t DEMO_SYNDROME = 0x0123456789ABCDEFull;
 #pragma pack(push, 1)
 struct Payload {
     std::uint64_t value;
-    std::uint32_t seq_num;
-    std::uint32_t pad;
+    std::uint32_t decoder_id; // selects which decoder handles this message
+    std::uint32_t seq_num;    // arrival flag
 };
 #pragma pack(pop)
 static_assert(sizeof(Payload) == 16, "Payload must be exactly 16 B");
+static_assert(offsetof(Payload, seq_num) + sizeof(Payload::seq_num) == sizeof(Payload),
+              "seq_num must be the last field in Payload");
+static_assert(offsetof(Payload, value) == 0,
+              "value must be first so a decoder can read the data from the frame's start");
+static_assert(offsetof(Payload, decoder_id) == 8, "decoder_id is at byte offset 8");
 
 /**
  * @brief Bytes of a Payload the caller and the coprocessor function may use.

diff --git a/runtime/lib/transport/cpu_verbs/base/CpuSessionBase.cpp b/runtime/lib/transport/cpu_verbs/base/CpuSessionBase.cpp
@@ -128,7 +128,6 @@ void CpuSessionBase<Role>::post_write(ibv_qp *qp, std::uint64_t cursor, bool inl
                                       bool signaled) {
     auto *send = send_payload(); // value already written by the caller
     send->seq_num = static_cast<std::uint32_t>(cursor + 1);
-    send->pad = 0;
     ibv_sge sge{
         .addr = reinterpret_cast<std::uint64_t>(send),
         .length = sizeof(Payload), // 16 B on the wire, into slot's first 16 B

diff --git a/runtime/lib/transport/cpu_verbs/controller/CpuControllerSession.cpp b/runtime/lib/transport/cpu_verbs/controller/CpuControllerSession.cpp
@@ -64,12 +64,14 @@ void *CpuControllerSession::data_slot() {
     return &send_payload()->value;
 }
 
-void CpuControllerSession::write_data_slot(const void *src, std::uint64_t bytes) {
+void CpuControllerSession::write_data_slot(const void *src, std::uint64_t bytes,
+                                           std::uint32_t decoder_id) {
     RDMA_CHECK(bytes <= in_bytes_, "payload (%zu B) exceeds the %zu B committed for this round",
                static_cast<std::size_t>(bytes), static_cast<std::size_t>(in_bytes_));
     Payload *send = send_payload();
     send->value = 0;
     std::memcpy(&send->value, src, bytes);
+    send->decoder_id = decoder_id;
 }
 
 int CpuControllerSession::kick(std::uint32_t /*work_item_idx*/) {

diff --git a/runtime/lib/transport/cpu_verbs/controller/CpuControllerSession.hpp b/runtime/lib/transport/cpu_verbs/controller/CpuControllerSession.hpp
@@ -41,7 +41,7 @@ class CpuControllerSession : public CpuSessionBase<ControllerSession> {
                           std::uint64_t out_bytes) override;
     int kick(std::uint32_t work_item_idx = 0) override;
     void *data_slot() override;
-    void write_data_slot(const void *src, std::uint64_t bytes) override;
+    void write_data_slot(const void *src, std::uint64_t bytes, std::uint32_t decoder_id) override;
 
   protected:
     bool oob_listens() const override { return false; }

diff --git a/runtime/lib/transport/cpu_verbs/coprocessor/CpuCoprocessorSession.cpp b/runtime/lib/transport/cpu_verbs/coprocessor/CpuCoprocessorSession.cpp
@@ -98,10 +98,11 @@ void CpuCoprocessorSession::run(std::stop_token st) {
         last_word_.store(r->value, std::memory_order_relaxed);
         completed_.fetch_add(1, std::memory_order_release);
         Payload *send = send_payload();
-        send->value = 0; // deterministic high bytes when the result is shorter
+        send->value = 0;
+        send->decoder_id = r->decoder_id;
         if (coproc_fn_) {
-            const std::size_t nb = coproc_fn_(&r->value, PAYLOAD_DATA_BYTES, &send->value,
-                                              PAYLOAD_DATA_BYTES, coproc_ctx_);
+            const std::size_t nb =
+                coproc_fn_(r, sizeof(Payload), &send->value, PAYLOAD_DATA_BYTES, coproc_ctx_);
             RDMA_CHECK(nb > 0 && nb <= PAYLOAD_DATA_BYTES,
                        "coprocessor function wrote %zu bytes, expected 1..%zu", nb,
                        PAYLOAD_DATA_BYTES);

diff --git a/runtime/lib/transport/cpu_verbs/coprocessor/CpuCoprocessorSession.hpp b/runtime/lib/transport/cpu_verbs/coprocessor/CpuCoprocessorSession.hpp
@@ -25,9 +25,10 @@
 
 namespace catalyst::transport::cpu_verbs {
 
-// Coprocessor role: receives messages, runs the coprocessor function, and
-// returns the result. The function is bound via set_coprocessor_fn; nullptr
-// selects the built-in echo.
+// Coprocessor role: receives messages, runs the coprocessor function, and returns
+// the result. The function is bound via set_coprocessor_fn; nullptr selects the
+// built-in echo. Each message's decoder_id is handed to the function, which may
+// serve several codes and dispatch on it, or ignore it if it serves only one.
 class CpuCoprocessorSession : public CpuSessionBase<CoprocessorSession> {
     using Base = CpuSessionBase<CoprocessorSession>;
 

diff --git a/runtime/lib/transport/cpu_verbs/coprocessor/coprocessor_functions/steane_decoder_fn.cpp b/runtime/lib/transport/cpu_verbs/coprocessor/coprocessor_functions/steane_decoder_fn.cpp
@@ -49,6 +49,10 @@ constexpr std::int64_t STEANE_SYNDROME_TO_QUBIT[1u << STEANE_CHECKS] = {-1, 6, 4
  * the wire does not carry; a decoder therefore has to know its own code's check
  * count.
  */
+// `in` is the request frame; its leading bytes are the syndrome. The frame's
+// decoder_id (a uint32 at byte offset 8) is not read: the [[7,1,3]] Steane code has
+// Hx == Hz, so one table serves both the X and Z checks. A code whose matrices differ
+// would read that field and switch on it here.
 extern "C" std::size_t steane_coprocessor(const void *in, std::size_t in_len, void *out,
                                           std::size_t out_cap, void * /*ctx*/) {
     if (in == nullptr || out == nullptr || in_len < STEANE_CHECKS ||