feat: implemented segmentation-paging simulator #62
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sharvil-lade
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Description
The simulator translates logical addresses into physical addresses through a hybrid segmentation and paging approach.
Each process is first divided into segments, representing logical modules like code, data, and stack.
Every segment is then further divided into fixed-size pages for efficient memory allocation.
Finally, these pages are mapped to physical memory frames, combining segmentation’s modularity with paging’s space efficiency.
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