mb/google/*: Add CFR options for Intel ME HECI1 and PAVP#27
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movr4x wants to merge 4 commits intoMrChromebox:MrChromebox-2512from
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mb/google/*: Add CFR options for Intel ME HECI1 and PAVP#27movr4x wants to merge 4 commits intoMrChromebox:MrChromebox-2512from
movr4x wants to merge 4 commits intoMrChromebox:MrChromebox-2512from
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Kconfig DISABLE_HECI1_AT_PRE_BOOT is a compile-time only option. This commit adds support for a run-time configurable CFR, where Kconfig DISABLE_HECI1_AT_PRE_BOOT is used as a default value, and updates SoC code to use this new CFR instead of Kconfig. Signed-off-by: Lukasz Kutyla <luk.kutyla@gmail.com>
Allow users to enable/disable HECI1 via CFR options menu. Signed-off-by: Lukasz Kutyla <luk.kutyla@gmail.com>
Kconfig PAVP is a compile-time only option. This commit adds support for a run-time configurable CFR, where Kconfig PAVP is used as a default value, and updates SoC code to use this new CFR instead of Kconfig. Signed-off-by: Lukasz Kutyla <luk.kutyla@gmail.com>
Allow users to enable/disable PAVP via CFR options menu. Signed-off-by: Lukasz Kutyla <luk.kutyla@gmail.com>
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what's the use of enabling/disabling PAVP? I'm not a huge fan of adding options just to have them |
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It is available in Intel common Kconfig, so I have thought that it could be useful to also have it as a run-time configurable CFR, just like HECI1 device, especially since it requires HECI1 device to operate (AFAIK). However, I am not sure if PAVP even works in Google boards (i.e. disabled at a lower level, so changing FSP-S param has no effect) or if this is some Linux related limitation. Ideally I would need Windows to confirm, but at the moment I cannot test this. If you want, then I can drop this. |
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Allow users to enable/disable HECI1 and PAVP via CFR options menu.
Kconfig DISABLE_HECI1_AT_PRE_BOOT and PAVP are compile-time only options.
This adds support for a run-time configurable CFR, where Kconfig is used as a default value, and updates SoC code to use this new CFR instead of Kconfig.
Should address issues like:
MrChromebox/firmware#887
I could not find any reference to
CONFIG(PAVP)in Tigerlake SoC code, so I did not include PAVP CFR for VOLTEER. FSP-S code also does not touchPavpEnableparam (it is available). We can change this.There are Google boards with Pantherlake SoC, OCELOT/FATCAT, that could also use CFR for both HECI1 and PAVP, but they do not have CFR/
cfr.c.You will have to verify if all looks ok, as I can only test Skylake/Kabylake (FIZZ).
It would be possible to add few other CFRs for controlling ME remote functionality like AMT/AMT SoL/ASF/Manageability Mode, but non-vPro firmwares usually lack such features anyway.
Also, not sure if PAVP works in Linux for Google boards. I have tried to extract some info, but cannot see any difference between PAVP disabled/enabled. There is a possibility that it is disabled at a lower level like Intel PTT (iTPM), at least for FIZZ.
With Intel ME and HECI1 always enabled, and only toggling PAVP, I am getting the same results: