A project using Amaranth HDL for testing a particle detector ASIC

Overview

This project leverages the Amaranth HDL to test a particle detector ASIC design. It includes a bunch of counters to count pulses from the detector, and a serial protocol to start/stop/reset and read the counters.

Features

• Written in Python using Amaranth HDL.
• Simulates and verifies the counter's behavior.
• Designed for integration with particle detector systems.

Requirements

• Python 3.10<=>3.14
• Amaranth HDL library.

Getting Started

You first need install Lattice iCE40 toolchain (yosys, nextpnr, icestorm) and iverilog for simulation. On Fedora, you can install them using:

sudo dnf install iverilog icestorm yosys nextpnr python3-pip

You can also have a look to the OSS CAD Suite project, which provides pre-built toolchain binaries for various platforms.

1. Clone the repository:

   git clone <repository_url>
   cd ASIC_Counter

2. Install python dependencies using uv:

   uv venv
   uv pip install -e .[dev]

3. Run tests:

   uv run pytest

4. Build and program the FPGA:

   uv run python -m asic_counter.top --program

5. Optionally, specify the number of counter channels:

   uv run python -m asic_counter.top --program --channels-count 16

License

This project is licensed under the GPL-3.0-or-later License. See the LICENSE file for details.