- Low-level computational machine design
- Feedback-driven control and computation
- Hardware-software interface boundaries
- Fault tolerant and self-correcting architectures
- Gate-level and threshold-based learning systems
- Algorithm design under hardware constraints
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Undergraduate Student ๐
- New Delhi, India
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02:44
(UTC +05:30) - https://KARAN-D05.github.io
- in/karan-diwan05
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Computing_Machinery_from_Scratch
Computing_Machinery_from_Scratch PublicStarted as an idea which kept evolving into a better and more advanced fault-tolerant 400+ logic gate autonomous arithmetic computing machine which then eventually evolved into a machine that can eโฆ
Verilog 1
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Gate-Level-Cybernetic-Classifier
Gate-Level-Cybernetic-Classifier PublicThis project explores how adaptive behavior and learning-like dynamics can emerge from purely deterministic gate-level systems. It evolves from strict Boolean matching to score-based decision makinโฆ
Verilog 2
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8-Bit-Computer
8-Bit-Computer PublicIndependently designing, testing and building an 8-Bit computer to explore how computers work fundamentally at gate level. Implemented various digital modules like Programmable ROM, address decoderโฆ
Verilog 1
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Artificial-Neuron
Artificial-Neuron PublicThis project implements a basic McCullochโPitts artificial neuron. The current versions supports two binary inputs, a programmable threshold and inhibitory weights allowing it to emulate logic funcโฆ
Verilog
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TopoCore
TopoCore PublicTopoCore is an experimental spatial execution architecture where programs exist as traversable 2D layouts rather than linear instruction streams. Inspired by Befunge, semiotics, and semasiographic โฆ
Befunge
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