Timing model V4 by hausdinge · Pull Request #562 · FPGA-Research/FABulous

hausdinge · 2025-12-15T02:32:31Z

This is the new timing model.
Its mostly done and the interface wont change much anymore.
Still i want to polish it and add some minor improvements and optimizations.

KelvinChung2000

I saw you have included the repo of the f4fpga_sdf_timing. See whether we can install that instead. I personally like Lark as the parser, as it is clean and pleasant to use, but building the SDF grammar again is probably a waste of time. If there is a strong desire or the parsing becomes the bottleneck, we can move on later.

Also, the whole timing_model should go under the fabric_cad folder.

hausdinge · 2025-12-15T10:09:39Z

Regarding to f4fpga_sdf_timing i included it because they had issues in their lexer i noticed also because there is no update since three years and to avoid breaking changes. Lark seems more clear true, they used PLY and the recommendation of them is to include the PLY files directly and not as a package too.

Parsing is not the bottleneck its only done once per Tile and takes around 3s.
But since i havent seen any other SDF parser it could actually be worth it to make a new one with Lark in the future.

KelvinChung2000 · 2025-12-15T15:06:04Z

Instead of embedding it directly, we could fork it and publish it ourselves with the necessary fixes. Alternatively, you can embed it as a subrepo. Any thoughts @EverythingElseWasAlreadyTaken

EverythingElseWasAlreadyTaken · 2025-12-15T17:54:55Z

Instead of embedding it directly, we could fork it and publish it ourselves with the necessary fixes. Alternatively, you can embed it as a subrepo. Any thoughts @EverythingElseWasAlreadyTaken

Yes, we should do a fork and maintain it separately.
This also makes the ownership clear.

If it's only a python script, we don't even need a subrepo, you can just use it as dependency and specify the git link.

EverythingElseWasAlreadyTaken · 2025-12-15T18:01:10Z

I've created a fork here:
https://github.com/FPGA-Research/f4pga-sdf-timing

Please do a PR there.

hausdinge · 2025-12-15T18:16:53Z

I've created a fork here: https://github.com/FPGA-Research/f4pga-sdf-timing

Please do a PR there.

Okay. So its only a python script three, four files.

read-the-docs-community · 2026-02-22T15:50:42Z

Documentation build overview

📚 FABulous | 🛠️ Build #32186029 | 📁 Comparing 6d33ce6 against latest (c48bed6)

🔍 Preview build

Show files changed (44 files in total): 📝 15 modified | ➕ 29 added | ➖ 0 deleted

File	Status
genindex.html	📝 modified
py-modindex.html	📝 modified
_modules/index.html	📝 modified
user_guide/index.html	📝 modified
_modules/fabulous/fabulous_api.html	📝 modified
_modules/fabulous/fabulous_settings.html	📝 modified
user_guide/building_doc/index.html	📝 modified
user_guide/building_doc/timing_characterization.html	➕ added
user_guide/cli_doc/fabulous_variable.html	📝 modified
_modules/fabulous/fabric_cad/gen_npnr_model.html	📝 modified
_modules/fabulous/fabulous_cli/fabulous_cli.html	📝 modified
generated_doc/fabulous/fabric_cad/index.html	📝 modified
generated_doc/fabulous/fabulous_api/index.html	📝 modified
generated_doc/fabulous/fabulous_settings/index.html	📝 modified
_modules/fabulous/fabric_cad/timing_model/FABulous_timing_model.html	➕ added
_modules/fabulous/fabric_cad/timing_model/FABulous_timing_model_interface.html	➕ added
_modules/fabulous/fabric_cad/timing_model/models.html	➕ added
generated_doc/fabulous/fabric_cad/gen_npnr_model/index.html	📝 modified
generated_doc/fabulous/fabric_cad/timing_model/index.html	➕ added
generated_doc/fabulous/fabulous_cli/fabulous_cli/index.html	📝 modified
_modules/fabulous/fabric_cad/timing_model/hdlnx/hdlnx_timing_model.html	➕ added
_modules/fabulous/fabric_cad/timing_model/hdlnx/verilog_gate_level.html	➕ added
_modules/fabulous/fabric_cad/timing_model/tools/specification.html	➕ added
generated_doc/fabulous/fabric_cad/timing_model/FABulous_timing_model/index.html	➕ added
generated_doc/fabulous/fabric_cad/timing_model/FABulous_timing_model_interface/index.html	➕ added
generated_doc/fabulous/fabric_cad/timing_model/hdlnx/index.html	➕ added
generated_doc/fabulous/fabric_cad/timing_model/models/index.html	➕ added
generated_doc/fabulous/fabric_cad/timing_model/tools/index.html	➕ added
_modules/fabulous/fabric_cad/timing_model/hdlnx/sdfnx/sdf_to_graph.html	➕ added
_modules/fabulous/fabric_cad/timing_model/hdlnx/sdfnx/sdf_to_graph_base.html	➕ added
_modules/fabulous/fabric_cad/timing_model/hdlnx/sdfnx/timing_graph.html	➕ added
_modules/fabulous/fabric_cad/timing_model/tools/sta_tools/opensta.html	➕ added
_modules/fabulous/fabric_cad/timing_model/tools/synth_tools/yosys.html	➕ added
generated_doc/fabulous/fabric_cad/timing_model/hdlnx/hdlnx_timing_model/index.html	➕ added
generated_doc/fabulous/fabric_cad/timing_model/hdlnx/sdfnx/index.html	➕ added
generated_doc/fabulous/fabric_cad/timing_model/hdlnx/verilog_gate_level/index.html	➕ added
generated_doc/fabulous/fabric_cad/timing_model/tools/specification/index.html	➕ added
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generated_doc/fabulous/fabric_cad/timing_model/hdlnx/sdfnx/sdf_to_graph/index.html	➕ added
generated_doc/fabulous/fabric_cad/timing_model/hdlnx/sdfnx/sdf_to_graph_base/index.html	➕ added
generated_doc/fabulous/fabric_cad/timing_model/hdlnx/sdfnx/timing_graph/index.html	➕ added
generated_doc/fabulous/fabric_cad/timing_model/tools/sta_tools/opensta/index.html	➕ added
generated_doc/fabulous/fabric_cad/timing_model/tools/synth_tools/yosys/index.html	➕ added

hausdinge · 2026-02-22T21:33:58Z

I rebased it to main.

KelvinChung2000 · 2026-02-23T09:34:42Z

I have forked https://github.com/FPGA-Research/f4pga-sdf-timing. Can you update to do repo-based install (doc)? Include fixes that you need. I have also done a lark version for fun https://github.com/KelvinChung2000/sdf-timing-lark.

hausdinge · 2026-02-23T12:54:04Z

I have forked https://github.com/FPGA-Research/f4pga-sdf-timing. Can you update to do repo-based install (doc)? Include fixes that you need. I have also done a lark version for fun https://github.com/KelvinChung2000/sdf-timing-lark.

So i could also use the lark version have you included my changes there?

KelvinChung2000 · 2026-02-23T12:58:07Z

I have forked https://github.com/FPGA-Research/f4pga-sdf-timing. Can you update to do repo-based install (doc)? Include fixes that you need. I have also done a lark version for fun https://github.com/KelvinChung2000/sdf-timing-lark.

So i could also use the lark version have you included my changes there?

The Lark version is with the fixes. If you do decide to go with the Lark version, do a bit more testing. Otherwise just copy your fixes to the F4PGA SDF fork.

hausdinge · 2026-02-23T13:01:50Z

I have forked https://github.com/FPGA-Research/f4pga-sdf-timing. Can you update to do repo-based install (doc)? Include fixes that you need. I have also done a lark version for fun https://github.com/KelvinChung2000/sdf-timing-lark.

So i could also use the lark version have you included my changes there?

The Lark version is with the fixes. If you do decide to go with the Lark version, do a bit more testing. Otherwise just copy your fixes to the F4PGA SDF fork.

yes i will do it.

hausdinge · 2026-02-23T14:35:23Z

I have forked https://github.com/FPGA-Research/f4pga-sdf-timing. Can you update to do repo-based install (doc)? Include fixes that you need. I have also done a lark version for fun https://github.com/KelvinChung2000/sdf-timing-lark.

So i could also use the lark version have you included my changes there?

The Lark version is with the fixes. If you do decide to go with the Lark version, do a bit more testing. Otherwise just copy your fixes to the F4PGA SDF fork.

yes i will do it.

Also your lark version has the exactly the same interface right?

IAmMarcelJung

Next tiny batch

fix: update Doc class template

hausdinge · 2026-03-17T12:03:51Z

One general Question: So the GDS flow works now by auto detecting
The PDK if i dont specify it in the .env file.

But what should i do to point to the correct hash
for the PDK, currently the timing model does not use
the auto detecting feature.

Do i have to do something like:
get_context().pdk_root/ciel/get_context().pdk_hash/.. or similar?

KelvinChung2000 · 2026-03-17T12:23:19Z

If you don't specify the PDK, you basically don't get the GDS flow. Also, the auto detect will auto-enable the PDK. You should not need to use the hash at all since ciel will have a symbolic link that links to the current active PDK.

So path.resolve(get_context().pdk_root/get_context().pdk).absolute() (or simlar syntax) should point to where you need

mole99

Thanks to the latest patches, the timing model can now be created for the Tiny Tapeout fabric 🎉

To get this to work with my LibreLane plugin and the "tiny" tile library, I had to copy some files to different locations in order for the flow to succeed.
I would appreciate it if the timing model generator did not assume the location of the files, but instead used absolute paths.
This can be achieved by passing a dict with all the file paths for each tile to FABulousTimingModelInterface:

sources = {
  "LUT4AB": {
    "rtl": [
      "path/to/LUT4AB.v",
      "path/to/LUT4AB_switch_matrix.v",
      "path/to/LUT4AB_ConfigMem.v",
      "path/to/primitives.v",
      "path/to/models.v",
    ],
    "spef": "path/to/nom/LUT4AB.nom.spef",
    "nl": "path/to/LUT4AB.nl.v",
  }
  ...
}

You would specify the RTL/SPEF/NL files in fabulous_api.py, and I can do the same in my LibreLane plugin.
This also allows us to change the interconnect corner (nom/min/max) of the SPEF.
Another benefit is that this method only reads the RTL needed for the current tile. Previously, all the RTL for all tiles would be read.

hausdinge · 2026-03-17T14:07:51Z

Thanks to the latest patches, the timing model can now be created for the Tiny Tapeout fabric 🎉

To get this to work with my LibreLane plugin and the "tiny" tile library, I had to copy some files to different locations in order for the flow to succeed. I would appreciate it if the timing model generator did not assume the location of the files, but instead used absolute paths. This can be achieved by passing a dict with all the file paths for each tile to FABulousTimingModelInterface:
sources = {
  "LUT4AB": {
    "rtl": [
      "path/to/LUT4AB.v",
      "path/to/LUT4AB_switch_matrix.v",
      "path/to/LUT4AB_ConfigMem.v",
      "path/to/primitives.v",
      "path/to/models.v",
    ],
    "spef": "path/to/nom/LUT4AB.nom.spef",
    "nl": "path/to/LUT4AB.nl.v",
  }
  ...
}
You would specify the RTL/SPEF/NL files in fabulous_api.py, and I can do the same in my LibreLane plugin. This also allows us to change the interconnect corner (nom/min/max) of the SPEF. Another benefit is that this method only reads the RTL needed for the current tile. Previously, all the RTL for all tiles would be read.

I could do that.
That meas we still have the default behavior where files
are read from the project-dir for easy scripting but if the user
specifies a manual config with this custom_per_tile_source_files set
then we overwrite RTL, RC, and NL. For that i would remove:
custom_per_tile_netlist_files, custom_per_tile_rc_files since
this will be then covered by custom_per_tile_source_files.
But the context must still be loaded means at least the FABRIC
object must be set.

mole99 · 2026-03-17T14:30:38Z

@hausdinge Great!

You can still have the same behavior with FABulous CLI. But instead of searching for the files inside of the timing model generator, you do it outside.

The idea is that you remove these things from the generator:

        # Find all the Verilog files for the tile, excluding certain 
        # directories that are not relevant for synthesis.

        exclude_dir_patterns: list[str] = ["macro", "user_design", "Test"]
        self.verilog_files: list[Path] = self._find_matching_files(
            self.tm_config.project_dir, r".*\.v$", exclude_dir_patterns
        )

And move them outside to fabulous_api.py and then pass the file paths to FABulousTimingModelInterface.

This is not a feature that needs to be exposed to the user. My LibreLane plugin calls the FABulous functions directly, meaning I can pass the file paths to FABulousTimingModelInterface as well.

…-pdk from ciel

hausdinge · 2026-03-18T02:22:47Z

@hausdinge Great!

You can still have the same behavior with FABulous CLI. But instead of searching for the files inside of the timing model generator, you do it outside.

The idea is that you remove these things from the generator:
        # Find all the Verilog files for the tile, excluding certain 
        # directories that are not relevant for synthesis.

        exclude_dir_patterns: list[str] = ["macro", "user_design", "Test"]
        self.verilog_files: list[Path] = self._find_matching_files(
            self.tm_config.project_dir, r".*\.v$", exclude_dir_patterns
        )
And move them outside to fabulous_api.py and then pass the file paths to FABulousTimingModelInterface.

This is not a feature that needs to be exposed to the user. My LibreLane plugin calls the FABulous functions directly, meaning I can pass the file paths to FABulousTimingModelInterface as well.

Ah okay.
So i did it now that you can define it in the manual config for FABulousTimingModelInterface
The JSON template woul look like:

{
    "project_dir": "/home/timing_model_v4/FABulous/demo_mpw5",
    "liberty_files": "./demo_mpw5/sky130_fd_sc_hd__tt_025C_1v80.lib",
    "min_buf_cell_and_ports": "sky130_fd_sc_hd__buf_1 A X",
    "synth_executable": "/nix/store//bin/yosys",
    "sta_executable": "/nix/store/744j2gyd0s7pvww7nm1fw7z9500bh8y5-opensta/bin/sta",
    "techmap_files": ["./demo_mpw5/latch_map.v", "./demo_mpw5/tribuff_map.v"],
    "tiehi_cell_and_port": null,
    "tielo_cell_and_port": null,
    "custom_per_tile_source_files": {
        "RAM_IO": {
            "netlist_file": "./demo_mpw5/Tile/RAM_IO/phys/RAM_IO.v",
            "rc_file": "./demo_mpw5/Tile/RAM_IO/phys/RAM_IO.spef",
            "rtl_files": [
                "./demo_mpw5/Tile/RAM_IO/RAM_IO.v",
                "./demo_mpw5/Tile/RAM_IO/RAM_IO_switch_matrix.v",
                "./demo_mpw5/Tile/RAM_IO/RAM_IO_ConfigMem.v",
                "./demo_mpw5/Tile/RAM_IO/OutPass4_frame_config_mux.v",
                "./demo_mpw5/Tile/RAM_IO/InPass4_frame_config_mux.v",
                "./demo_mpw5/Tile/RAM_IO/Config_access.v",
                "./demo_mpw5/Fabric/models_pack.v"
            ]
        }, ...

So every entry overwrites the default paths in the project dir.
In python use manual_config: TimingModelConfig for the Configuration.

mole99

I've updated my LibreLane plugin to specify the paths, and it works without any problems!

Thanks for implementing the changes, @hausdinge.

EverythingElseWasAlreadyTaken

Overall looks good, just a few minor comments.
Would be nice if your test cases could get at least some basic comments.

Also, please rebase when #655 is merged and run pre-commit again.
There are quite a few formatting / lining issues, that will be fixed with this.

Also, there are still quite some open/unresolved comments from others , that might need further discussion.

fix: lint issues and doc strings

hausdinge · 2026-03-26T02:00:52Z

When i did the commit, pre-commit hooks
were only applied for fabulous_api and fabulous_cli.

All the errors for all files can only be seen by typing: uv run pre-commit run --all-files,
at least for me...

KelvinChung2000 · 2026-03-26T10:03:44Z

Because by default, it only checks the files that need committing.

hausdinge · 2026-03-26T12:29:42Z

Because by default, it only checks the files that need committing.

Makes sense. It was just here an issue since pre-commit was not
working before.

… info

fix: timing model tests for pre-commit

KelvinChung2000 reviewed Dec 15, 2025

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EverythingElseWasAlreadyTaken added the waiting Issue is waits for other Issue / PR / ... label Dec 19, 2025

EverythingElseWasAlreadyTaken added Needs rebase This PR needs to be rebased before merged. and removed waiting Issue is waits for other Issue / PR / ... labels Feb 10, 2026

hausdinge force-pushed the timing_model branch from 9994d0e to 8189422 Compare February 22, 2026 15:49

hausdinge force-pushed the timing_model branch from 79927a4 to 9994d0e Compare February 22, 2026 17:19

hausdinge added 5 commits February 22, 2026 19:03

add timing modle v4

3a35c19

support any DSP tile, fix tile paths, move to fabric_cad

4d112c0

fix [0:0] issues in the netlist generation

2e2c4cd

improve runtime physical flow of factor 50

ad84b59

feature: tile external delays

46acac9

hausdinge force-pushed the timing_model branch from 9994d0e to 46acac9 Compare February 22, 2026 21:21

rebase to fabulous main

955da3f

regenerate uv.lock

b851c63

EverythingElseWasAlreadyTaken self-requested a review March 16, 2026 11:08

IAmMarcelJung reviewed Mar 16, 2026

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hausdinge added 3 commits March 16, 2026 22:09

Merge remote-tracking branch 'upstream/main' into timing_model

6bd3155

fix: sink, source twist in delay key

9f22241

Merge remote-tracking branch 'upstream/main' into timing_model

51f7c4e

fix: update Doc class template

mole99 suggested changes Mar 17, 2026

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hausdinge added 2 commits March 18, 2026 01:24

feat: support for non default location of Tile rtl code, support auto…

ffc1540

…-pdk from ciel

Merge remote-tracking branch 'upstream/main' into timing_model

0312295

mole99 approved these changes Mar 18, 2026

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EverythingElseWasAlreadyTaken reviewed Mar 19, 2026

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Merge remote-tracking branch 'upstream/main' into timing_model

7f01db3

fix: lint issues and doc strings

hausdinge added 9 commits March 26, 2026 13:33

refactor: resolve all lint and doc-string issues

348a42e

Merge remote-tracking branch 'upstream/main' into timing_model

ddcd443

fix: some comments and code-style

0cefeed

fix: timing model tests naming changes

a7ca21a

fix: remove all os imports improve comments

2512570

refactor: rename delay_path to single_delay. Remove unused delay path…

6ccf6d2

… info

doc: add doc for timing model

ce885de

fix: ignore ml and simulation files

38ef77c

Merge remote-tracking branch 'upstream/main' into timing_model

6d33ce6

fix: timing model tests for pre-commit

EverythingElseWasAlreadyTaken approved these changes Apr 17, 2026

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EverythingElseWasAlreadyTaken merged commit 09dba97 into FPGA-Research:main Apr 17, 2026
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