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[caravel] make addr in wb gpio byte addr, not word addr Scala CI #107: Commit cb27778 pushed by tjarker
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[caravel] add morse Scala CI #106: Commit 03d354a pushed by tjarker
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[caravel] use rf wrapper Scala CI #105: Commit 87a702f pushed by tjarker
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[caravel] fix address width for the RF Scala CI #104: Commit 019f1c9 pushed by schoeberl
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[caravel] add tnt's register file Scala CI #103: Commit f6d474f pushed by schoeberl
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change caravel address mapping, add wishbone gpio Scala CI #102: Commit c494a6c pushed by tjarker
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[caravel] add pipeline stage to wishbone into LerosCaravel systems Scala CI #101: Commit a5956da pushed by tjarker
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add verbose parameter to openram sram macro Scala CI #100: Commit 66277d3 pushed by tjarker
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[caravel] remove debug outputs, add dffram and SyncReadMem versions (… Scala CI #99: Commit 1ade9cd pushed by tjarker
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[caravel] disconnect la, swap DFFRAM to CF version Scala CI #98: Commit 9363dd1 pushed by tjarker
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add ponte-cli for UART to APB communication Scala CI #97: Commit 4a0a849 pushed by tjarker
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change caravel top to 2 leros subsystems Scala CI #96: Commit cb0498c pushed by tjarker
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fix error in tests Scala CI #95: Commit 533e2f1 pushed by tjarker
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change caravel leros io (add dbg and reduce wb_adr) Scala CI #94: Commit 1ec5806 pushed by tjarker
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fix leros uart (add rx buffer clear by writing to status reg) Scala CI #93: Commit e240f4f pushed by tjarker
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add wishbone mux and caravel tests Scala CI #92: Commit 51c2d7f pushed by tjarker
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Leros Caravel has 8 IO pins Scala CI #91: Commit e0145bd pushed by schoeberl
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add reg for out select in ApbMux and change CF SRAM interface Scala CI #90: Commit 45ceafc pushed by tjarker
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fix apb combinatorial path Scala CI #89: Commit 772e8b7 pushed by tjarker
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change cf sram interface (no wb) Scala CI #88: Commit 7f71e50 pushed by tjarker
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leros caravel project has 8 gpio pins Scala CI #87: Commit 9cb86ad pushed by tjarker
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1h 18m 30s
fix tests Scala CI #86: Commit 4ebf654 pushed by tjarker
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fix dtu_ss io regression Scala CI #85: Commit 61de83d pushed by tjarker
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add chipfoundry sram, change dtu_ss baud and freq, fix tests Scala CI #84: Commit 44cacdf pushed by tjarker
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rework memory factory and add dffram Scala CI #83: Commit a84fb13 pushed by tjarker
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