@@ -135,32 +135,18 @@ struct mc_t1s_data {
135135static int phy_mc_t1s_read (const struct device * dev , uint16_t reg , uint32_t * data )
136136{
137137 const struct mc_t1s_config * cfg = dev -> config ;
138- int ret ;
139138
140139 /* Make sure excessive bits 16-31 are reset */
141140 * data = 0U ;
142141
143- mdio_bus_enable (cfg -> mdio );
144-
145- ret = mdio_read (cfg -> mdio , cfg -> phy_addr , reg , (uint16_t * )data );
146-
147- mdio_bus_disable (cfg -> mdio );
148-
149- return ret ;
142+ return mdio_read (cfg -> mdio , cfg -> phy_addr , reg , (uint16_t * )data );
150143}
151144
152145static int phy_mc_t1s_write (const struct device * dev , uint16_t reg , uint32_t data )
153146{
154147 const struct mc_t1s_config * cfg = dev -> config ;
155- int ret ;
156-
157- mdio_bus_enable (cfg -> mdio );
158-
159- ret = mdio_write (cfg -> mdio , cfg -> phy_addr , reg , (uint16_t )data );
160148
161- mdio_bus_disable (cfg -> mdio );
162-
163- return ret ;
149+ return mdio_write (cfg -> mdio , cfg -> phy_addr , reg , (uint16_t )data );
164150}
165151
166152static int mdio_setup_c45_indirect_access (const struct device * dev , uint16_t devad , uint16_t reg )
@@ -192,20 +178,13 @@ static int phy_mc_t1s_c45_read(const struct device *dev, uint8_t devad, uint16_t
192178 return mdio_read_c45 (cfg -> mdio , cfg -> phy_addr , devad , reg , val );
193179 }
194180
195- mdio_bus_enable (cfg -> mdio );
196-
197181 /* Read C45 registers using C22 indirect access registers */
198182 ret = mdio_setup_c45_indirect_access (dev , devad , reg );
199183 if (ret < 0 ) {
200- mdio_bus_disable (cfg -> mdio );
201184 return ret ;
202185 }
203186
204- ret = mdio_read (cfg -> mdio , cfg -> phy_addr , MII_MMD_AADR , val );
205-
206- mdio_bus_disable (cfg -> mdio );
207-
208- return ret ;
187+ return mdio_read (cfg -> mdio , cfg -> phy_addr , MII_MMD_AADR , val );
209188}
210189
211190static int phy_mc_t1s_c45_write (const struct device * dev , uint8_t devad , uint16_t reg , uint16_t val )
@@ -219,20 +198,13 @@ static int phy_mc_t1s_c45_write(const struct device *dev, uint8_t devad, uint16_
219198 return mdio_write_c45 (cfg -> mdio , cfg -> phy_addr , devad , reg , val );
220199 }
221200
222- mdio_bus_enable (cfg -> mdio );
223-
224201 /* Write C45 registers using C22 indirect access registers */
225202 ret = mdio_setup_c45_indirect_access (dev , devad , reg );
226203 if (ret < 0 ) {
227- mdio_bus_disable (cfg -> mdio );
228204 return ret ;
229205 }
230206
231- ret = mdio_write (cfg -> mdio , cfg -> phy_addr , MII_MMD_AADR , val );
232-
233- mdio_bus_disable (cfg -> mdio );
234-
235- return ret ;
207+ return mdio_write (cfg -> mdio , cfg -> phy_addr , MII_MMD_AADR , val );
236208}
237209
238210static int phy_mc_t1s_get_link (const struct device * dev , struct phy_link_state * state )
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