Bank Register and Vsync IRQ on the PICO-56

[yonglak]

Is the banking register implemented at $7F08 ?
Is the VSYNC from the TMS9918A implemented to the 6502 IRQ ?

thanks

[visrealm]

Hi.
The bank register and additional RAM isn't implemented as I haven't used it in any real software.
The VDP VSYNC raises an interrupt in the interrupt controller (which is connected to the 6502 IRQ line). When any of the device interrupts are raised (VDP, VIA, PS/2, UART), the CPU interrupt line is asserted by the interrupt controller. The interrupt controller can then be queried at $7fdf to determine which device (or devices) are interrupting.

[yonglak]

Hi.
Thanks for the quick reply.

Below are just some of my use cases...

I've recently got the Applesoft+F800 monitor to run on the PICO-56 in ACIA mode.
Have to disable interruptI. I was trying to get the AmperArcade (using '&' token in Applesoft) TMS9918a code which was located at $8800 and it was treating $8000 and > as ram. Thus not working.

I've also managed to get the C64 basic to run in ACIA serial mode but have to disable the interrupt (SEI).
Just trying to get the Jiffy clock IRQ to seed the RND generator. Currently have to poll the 6522 T1 timer.

I'm think enabling the interrupt might cause the serial to not work well in some cases.