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nedsebnedseb
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style(wb55): Apply astyle formating rules
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2 files changed

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‎variants/STM32WBxx/WB55R(C-E-G)V/variant_STEAM32_WB55RG.cpp‎

Lines changed: 107 additions & 107 deletions
Original file line numberDiff line numberDiff line change
@@ -19,60 +19,60 @@
1919
// Pin number
2020
// Pin number
2121
const PinName digitalPin[] = {
22-
PC_4, // D0/A1
23-
PA_5, // D1/A3
24-
PC_5, // D2/A5
25-
PA_2, // D3/A0
26-
PA_4, // D4/A2
27-
PA_7, // D5
28-
PC_3, // D6
29-
PA_9, // D7
30-
PA_15, // D8
31-
PC_2, // D9
32-
PA_6, // D10/A4
33-
PA_8, // D11
34-
PC_6, // D12
35-
PB_13, // D13
36-
PB_14, // D14
37-
PB_15, // D15
38-
PE_4, // D16
39-
PC_1, // D17
40-
PC_0, // D18
41-
PB_2, // D19
42-
PD_0, // D20
43-
PB_8, // D21
44-
PB_9, // D22
45-
PC_13, // D23
46-
PB_12, // D24
47-
PB_0, // D25
48-
PD_1, // D26
49-
PB_6, // D27
50-
PB_7, // D28
51-
PC_10, // D29
52-
PH_3, // D30
53-
PC_11, // D31
54-
PC_12, // D32
55-
PA_0, // D33
56-
PA_3, // D34
57-
PA_10, // D35
58-
PA_12, // D36
59-
PB_1, // D37
60-
PB_10, // D38
61-
PB_11, // D39
62-
PA_11, // D40
63-
PB_4, // D41
64-
PB_5, // D42
65-
PA_1, // D43
22+
PC_4, // D0/A1
23+
PA_5, // D1/A3
24+
PC_5, // D2/A5
25+
PA_2, // D3/A0
26+
PA_4, // D4/A2
27+
PA_7, // D5
28+
PC_3, // D6
29+
PA_9, // D7
30+
PA_15, // D8
31+
PC_2, // D9
32+
PA_6, // D10/A4
33+
PA_8, // D11
34+
PC_6, // D12
35+
PB_13, // D13
36+
PB_14, // D14
37+
PB_15, // D15
38+
PE_4, // D16
39+
PC_1, // D17
40+
PC_0, // D18
41+
PB_2, // D19
42+
PD_0, // D20
43+
PB_8, // D21
44+
PB_9, // D22
45+
PC_13, // D23
46+
PB_12, // D24
47+
PB_0, // D25
48+
PD_1, // D26
49+
PB_6, // D27
50+
PB_7, // D28
51+
PC_10, // D29
52+
PH_3, // D30
53+
PC_11, // D31
54+
PC_12, // D32
55+
PA_0, // D33
56+
PA_3, // D34
57+
PA_10, // D35
58+
PA_12, // D36
59+
PB_1, // D37
60+
PB_10, // D38
61+
PB_11, // D39
62+
PA_11, // D40
63+
PB_4, // D41
64+
PB_5, // D42
65+
PA_1, // D43
6666
};
6767

6868
// Analog (Ax) pin number array
6969
const uint32_t analogInputPin[] = {
70-
3, // A0
71-
0, // A1
72-
4, // A2
73-
1, // A3
74-
10, // A4
75-
2 // A5
70+
3, // A0
71+
0, // A1
72+
4, // A2
73+
1, // A3
74+
10, // A4
75+
2 // A5
7676
};
7777

7878
// ----------------------------------------------------------------------------
@@ -87,72 +87,72 @@ extern "C" {
8787
*/
8888
WEAK void SystemClock_Config(void)
8989
{
90-
RCC_OscInitTypeDef RCC_OscInitStruct = {};
91-
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
92-
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
90+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
91+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
92+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
9393

94-
/* This prevents concurrent access to RCC registers by CPU2 (M0+) */
95-
hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
94+
/* This prevents concurrent access to RCC registers by CPU2 (M0+) */
95+
hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
9696

97-
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
98-
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
97+
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
98+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
9999

100-
/* This prevents the CPU2 (M0+) to disable the HSI48 oscillator */
101-
hsem_lock(CFG_HW_CLK48_CONFIG_SEMID, HSEM_LOCK_DEFAULT_RETRY);
100+
/* This prevents the CPU2 (M0+) to disable the HSI48 oscillator */
101+
hsem_lock(CFG_HW_CLK48_CONFIG_SEMID, HSEM_LOCK_DEFAULT_RETRY);
102102

103-
/* Initializes the CPU, AHB and APB busses clocks */
104-
RCC_OscInitStruct.OscillatorType =
105-
RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
106-
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
107-
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
108-
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
109-
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
110-
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
111-
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
112-
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
113-
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
114-
RCC_OscInitStruct.PLL.PLLN = 16;
115-
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
116-
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
117-
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
118-
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
119-
Error_Handler();
120-
}
103+
/* Initializes the CPU, AHB and APB busses clocks */
104+
RCC_OscInitStruct.OscillatorType =
105+
RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
106+
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
107+
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
108+
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
109+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
110+
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
111+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
112+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
113+
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
114+
RCC_OscInitStruct.PLL.PLLN = 16;
115+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
116+
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
117+
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
118+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
119+
Error_Handler();
120+
}
121121

122-
/* Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers */
123-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2 | RCC_CLOCKTYPE_HCLK |
124-
RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
125-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
126-
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
127-
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
128-
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
129-
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
130-
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
131-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
132-
Error_Handler();
133-
}
122+
/* Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers */
123+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2 | RCC_CLOCKTYPE_HCLK |
124+
RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
125+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
126+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
127+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
128+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
129+
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
130+
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
131+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
132+
Error_Handler();
133+
}
134134

135-
/* Initializes the peripherals clocks */
136-
/* RNG needs to be configured like in M0 core, i.e. with HSI48 */
137-
PeriphClkInitStruct.PeriphClockSelection =
138-
RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB;
139-
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
140-
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
141-
PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
142-
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
143-
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
144-
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
145-
Error_Handler();
146-
}
135+
/* Initializes the peripherals clocks */
136+
/* RNG needs to be configured like in M0 core, i.e. with HSI48 */
137+
PeriphClkInitStruct.PeriphClockSelection =
138+
RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB;
139+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
140+
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
141+
PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
142+
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
143+
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
144+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
145+
Error_Handler();
146+
}
147147

148-
LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
149-
LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
150-
LL_PWR_SMPS_Enable();
148+
LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
149+
LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
150+
LL_PWR_SMPS_Enable();
151151

152-
/* Select HSI as system clock source after Wake Up from Stop mode */
153-
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
152+
/* Select HSI as system clock source after Wake Up from Stop mode */
153+
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
154154

155-
hsem_unlock(CFG_HW_RCC_SEMID);
155+
hsem_unlock(CFG_HW_RCC_SEMID);
156156
}
157157

158158
#ifdef __cplusplus

‎variants/STM32WBxx/WB55R(C-E-G)V/variant_STEAM32_WB55RG.h‎

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -143,7 +143,7 @@
143143
#define LED4 PH3
144144

145145
#ifndef LED_BUILTIN
146-
#define LED_BUILTIN LED1
146+
#define LED_BUILTIN LED1
147147
#endif
148148

149149
#define LED_BLUE LED1
@@ -162,7 +162,7 @@
162162
#define UP_BUTTON GP6
163163

164164
#ifndef USER_BTN
165-
#define USER_BTN MENU_BUTTON
165+
#define USER_BTN MENU_BUTTON
166166
#endif
167167

168168
// SPI Definitions
@@ -178,24 +178,24 @@
178178
// Timer Definitions
179179
// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin
180180
#ifndef TIMER_TONE
181-
#define TIMER_TONE TIM16
181+
#define TIMER_TONE TIM16
182182
#endif
183183
#ifndef TIMER_SERVO
184-
#define TIMER_SERVO TIM17
184+
#define TIMER_SERVO TIM17
185185
#endif
186186

187187
// UART Definitions
188188
#ifndef SERIAL_UART_INSTANCE
189-
#define SERIAL_UART_INSTANCE 0 // Connected to ST-Link
189+
#define SERIAL_UART_INSTANCE 0 // Connected to ST-Link
190190
#endif
191191

192192
// Default pin used for 'Serial' instance (ex: ST-Link)
193193
// Mandatory for Firmata
194194
#ifndef PIN_SERIAL_RX
195-
#define PIN_SERIAL_RX SERIAL_RX
195+
#define PIN_SERIAL_RX SERIAL_RX
196196
#endif
197197
#ifndef PIN_SERIAL_TX
198-
#define PIN_SERIAL_TX SERIAL_TX
198+
#define PIN_SERIAL_TX SERIAL_TX
199199
#endif
200200

201201
// Only 512k provided for cpu1, so defined the FLASH_PAGE_NUMBER
@@ -204,7 +204,7 @@
204204

205205
// Extra HAL modules
206206
#if !defined(HAL_QSPI_MODULE_DISABLED)
207-
#define HAL_QSPI_MODULE_ENABLED
207+
#define HAL_QSPI_MODULE_ENABLED
208208
#endif
209209

210210
/* backward compatibility */
@@ -215,21 +215,21 @@
215215
*----------------------------------------------------------------------------*/
216216

217217
#ifdef __cplusplus
218-
// These serial port names are intended to allow libraries and architecture-neutral
219-
// sketches to automatically default to the correct port name for a particular type
220-
// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
221-
// the first hardware serial port whose RX/TX pins are not dedicated to another use.
222-
//
223-
// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
224-
//
225-
// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
226-
//
227-
// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
228-
//
229-
// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
230-
//
231-
// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
232-
// pins are NOT connected to anything by default.
233-
#define SERIAL_PORT_MONITOR Serial
234-
#define SERIAL_PORT_HARDWARE Serial1
218+
// These serial port names are intended to allow libraries and architecture-neutral
219+
// sketches to automatically default to the correct port name for a particular type
220+
// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
221+
// the first hardware serial port whose RX/TX pins are not dedicated to another use.
222+
//
223+
// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
224+
//
225+
// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
226+
//
227+
// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
228+
//
229+
// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
230+
//
231+
// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
232+
// pins are NOT connected to anything by default.
233+
#define SERIAL_PORT_MONITOR Serial
234+
#define SERIAL_PORT_HARDWARE Serial1
235235
#endif

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