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CAN
1 parent 1290de4 commit e7ef023

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8 files changed

+87
-161
lines changed

8 files changed

+87
-161
lines changed

‎examples/can-echo.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ fn main() -> ! {
6161
let tx = gpiob.pb9.into_alternate().speed(Speed::VeryHigh);
6262

6363
info!("-- Create CAN 1 instance");
64-
let mut can = dp.FDCAN1.fdcan(tx, rx, &mut rcc);
64+
let mut can = dp.FDCAN1.fdcan((tx, rx), &mut rcc);
6565
can.set_protocol_exception_handling(false);
6666

6767
info!("-- Configure nominal timing");

‎examples/uart-dma-rx.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ fn main() -> ! {
4848
//.USART2
4949
.USART3
5050
.usart(
51-
(tx, rx),
51+
(Some(tx), Some(rx)),
5252
FullConfig::default()
5353
.baudrate(115200.bps())
5454
.receiver_timeout_us(1000), // Timeout after 1ms

‎examples/uart-dma-tx.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -39,8 +39,8 @@ fn main() -> ! {
3939

4040
info!("Init UART");
4141
let gpioa = dp.GPIOA.split(&mut rcc);
42-
let tx = gpioa.pa2.into_alternate();
43-
let rx = gpioa.pa3;
42+
let tx = Some(gpioa.pa2.into_alternate());
43+
let rx = Some(gpioa.pa3);
4444
let mut usart = dp.USART2.usart((tx, rx), 115200.bps(), &mut rcc).unwrap();
4545

4646
let mut delay_syst = cp.SYST.delay(&rcc.clocks);

‎examples/uart-fifo.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ fn main() -> ! {
3636
let mut usart = dp
3737
.USART2
3838
.usart(
39-
(tx, rx),
39+
(Some(tx), Some(rx)),
4040
FullConfig::default()
4141
.baudrate(115200.bps())
4242
.fifo_enable()

‎examples/uart.rs‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -33,22 +33,22 @@ fn main() -> ! {
3333
let rx = gpioa.pa3.into_alternate();
3434
let mut usart = dp
3535
.USART2
36-
.usart(tx, rx, FullConfig::default(), &mut rcc)
36+
.usart(((Some(tx), Some(rx)), FullConfig::default(), &mut rcc)
3737
.unwrap();*/
3838
/*let gpioc = dp.GPIOC.split(&mut rcc);
3939
let tx = gpioc.pc4.into_alternate();
4040
let rx = gpioc.pc5.into_alternate();
4141
let mut usart = dp
4242
.USART1
43-
.usart((tx, rx), FullConfig::default(), &mut rcc)
43+
.usart(((Some(tx), Some(rx)), FullConfig::default(), &mut rcc)
4444
.unwrap();*/
4545

4646
let gpioc = dp.GPIOC.split(&mut rcc);
4747
let tx = gpioc.pc10.into_alternate();
4848
let rx = gpioc.pc11.into_alternate();
4949
let mut usart = dp
5050
.USART3
51-
.usart((tx, rx), FullConfig::default(), &mut rcc)
51+
.usart((Some(tx), Some(rx)), FullConfig::default(), &mut rcc)
5252
.unwrap();
5353

5454
writeln!(usart, "Hello USART3, yay!!\r\n").unwrap();

‎src/can.rs‎

Lines changed: 43 additions & 133 deletions
Original file line numberDiff line numberDiff line change
@@ -1,193 +1,103 @@
11
//! # Controller Area Network (CAN) Interface
22
//!
33
4+
use crate::gpio::alt::CanCommon;
45
use crate::rcc::{self, Rcc};
56

6-
mod sealed {
7-
/// A TX pin configured for CAN communication
8-
pub trait Tx<CAN> {}
9-
/// An RX pin configured for CAN communication
10-
pub trait Rx<CAN> {}
11-
}
7+
pub trait Instance: CanCommon + rcc::Instance + crate::Ptr {}
128

139
/// Storage type for the CAN controller
1410
#[derive(Debug)]
15-
pub struct Can<FDCAN> {
16-
rb: FDCAN,
11+
pub struct Can<CAN: Instance> {
12+
rb: CAN,
1713
}
1814
#[allow(dead_code)]
19-
impl<FDCAN> Can<FDCAN> {
15+
impl<CAN: Instance> Can<CAN> {
2016
/// Returns a reference to the inner peripheral
21-
fn inner(&self) -> &FDCAN {
17+
fn inner(&self) -> &CAN {
2218
&self.rb
2319
}
2420
}
2521

2622
/// Extension trait for CAN controller
27-
pub trait CanExt: Sized
23+
pub trait CanExt: Sized + Instance
2824
where
29-
Self: rcc::Instance,
3025
Can<Self>: fdcan::Instance,
3126
{
32-
fn fdcan<TX, RX>(
27+
fn fdcan(
3328
self,
34-
_tx: TX,
35-
_rx: RX,
29+
pins: (impl Into<Self::Tx>, impl Into<Self::Rx>),
3630
rcc: &mut Rcc,
37-
) -> fdcan::FdCan<Can<Self>, fdcan::ConfigMode>
38-
where
39-
TX: sealed::Tx<Self>,
40-
RX: sealed::Rx<Self>,
41-
{
31+
) -> fdcan::FdCan<Can<Self>, fdcan::ConfigMode> {
4232
Self::enable(rcc);
33+
let _pins = (pins.0.into(), pins.1.into());
4334

4435
self.fdcan_unchecked()
4536
}
4637

4738
fn fdcan_unchecked(self) -> fdcan::FdCan<Can<Self>, fdcan::ConfigMode>;
4839
}
49-
/// Implements sealed::{Tx,Rx} for pins associated with a CAN peripheral
50-
macro_rules! pins {
51-
($PER:ident =>
52-
(tx: [ $($( #[ $pmetatx:meta ] )* $tx:ident<$txaf:ident>),+ $(,)? ],
53-
rx: [ $($( #[ $pmetarx:meta ] )* $rx:ident<$rxaf:ident>),+ $(,)? ])) => {
54-
$(
55-
$( #[ $pmetatx ] )*
56-
impl sealed::Tx<$PER> for $tx<$txaf> {}
57-
)+
58-
$(
59-
$( #[ $pmetarx ] )*
60-
impl sealed::Rx<$PER> for $rx<$rxaf> {}
61-
)+
62-
};
40+
41+
impl<CAN: Instance> Can<CAN>
42+
where
43+
Self: fdcan::message_ram::Instance,
44+
{
45+
pub fn new(rb: CAN) -> fdcan::FdCan<Self, fdcan::ConfigMode> {
46+
fdcan::FdCan::new(Self { rb }).into_config_mode()
47+
}
48+
}
49+
50+
unsafe impl<CAN: Instance> fdcan::Instance for Can<CAN>
51+
where
52+
Self: fdcan::message_ram::Instance,
53+
{
54+
const REGISTERS: *mut fdcan::RegisterBlock = CAN::PTR as *mut _;
55+
}
56+
57+
impl<CAN: Instance> CanExt for CAN
58+
where
59+
Can<Self>: fdcan::message_ram::Instance,
60+
{
61+
fn fdcan_unchecked(self) -> fdcan::FdCan<Can<Self>, fdcan::ConfigMode> {
62+
Can::new(self)
63+
}
6364
}
6465

6566
mod fdcan1 {
66-
use super::sealed;
67-
use super::{Can, CanExt};
68-
use crate::gpio::{AF9, PA11, PA12, PB8, PB9, PD0, PD1};
67+
use super::{Can, Instance};
6968
use crate::stm32::FDCAN1;
7069
use fdcan;
7170

72-
// All STM32G4 models with CAN support these pins
73-
pins! {
74-
FDCAN1 => (
75-
tx: [
76-
PA12<AF9>,
77-
PB9<AF9>,
78-
PD1<AF9>,
79-
],
80-
rx: [
81-
PA11<AF9>,
82-
PB8<AF9>,
83-
PD0<AF9>,
84-
]
85-
)
86-
}
71+
impl Instance for FDCAN1 {}
8772

88-
impl Can<FDCAN1> {
89-
pub fn fdcan1(rb: FDCAN1) -> fdcan::FdCan<Self, fdcan::ConfigMode> {
90-
fdcan::FdCan::new(Self { rb }).into_config_mode()
91-
}
92-
}
93-
impl CanExt for FDCAN1 {
94-
fn fdcan_unchecked(self) -> fdcan::FdCan<Can<Self>, fdcan::ConfigMode> {
95-
Can::fdcan1(self)
96-
}
97-
}
98-
unsafe impl fdcan::Instance for Can<FDCAN1> {
99-
const REGISTERS: *mut fdcan::RegisterBlock = FDCAN1::ptr() as *mut _;
100-
}
10173
unsafe impl fdcan::message_ram::Instance for Can<FDCAN1> {
10274
const MSG_RAM: *mut fdcan::message_ram::RegisterBlock = (0x4000_a400 as *mut _);
10375
}
10476
}
10577

106-
#[cfg(any(
107-
feature = "stm32g473",
108-
feature = "stm32g474",
109-
feature = "stm32g483",
110-
feature = "stm32g484",
111-
feature = "stm32g491",
112-
feature = "stm32g4a1",
113-
))]
78+
#[cfg(feature = "fdcan2")]
11479
mod fdcan2 {
115-
use super::sealed;
116-
use super::{Can, CanExt};
117-
use crate::gpio::{AF9, PB12, PB13, PB5, PB6};
80+
use super::{Can, Instance};
11881
use crate::stm32::FDCAN2;
11982
use fdcan;
12083
use fdcan::message_ram;
12184

122-
pins! {
123-
FDCAN2 => (
124-
tx: [
125-
PB6<AF9>,
126-
PB13<AF9>,
127-
],
128-
rx: [
129-
PB5<AF9>,
130-
PB12<AF9>,
131-
])
132-
}
85+
impl Instance for FDCAN2 {}
13386

134-
impl Can<FDCAN2> {
135-
pub fn fdcan2(rb: FDCAN2) -> fdcan::FdCan<Self, fdcan::ConfigMode> {
136-
fdcan::FdCan::new(Self { rb }).into_config_mode()
137-
}
138-
}
139-
impl CanExt for FDCAN2 {
140-
fn fdcan_unchecked(self) -> fdcan::FdCan<Can<Self>, fdcan::ConfigMode> {
141-
Can::fdcan2(self)
142-
}
143-
}
144-
unsafe impl fdcan::Instance for Can<FDCAN2> {
145-
const REGISTERS: *mut fdcan::RegisterBlock = FDCAN2::ptr() as *mut _;
146-
}
14787
unsafe impl fdcan::message_ram::Instance for Can<FDCAN2> {
14888
const MSG_RAM: *mut message_ram::RegisterBlock = (0x4000_a750 as *mut _);
14989
}
15090
}
15191

152-
#[cfg(any(
153-
feature = "stm32g473",
154-
feature = "stm32g474",
155-
feature = "stm32g483",
156-
feature = "stm32g484",
157-
))]
92+
#[cfg(feature = "fdcan3")]
15893
mod fdcan3 {
159-
use super::sealed;
160-
use super::{Can, CanExt};
161-
use crate::gpio::{AF11, PA15, PA8, PB3, PB4};
94+
use super::{Can, Instance};
16295
use crate::stm32::FDCAN3;
16396
use fdcan;
16497
use fdcan::message_ram;
16598

166-
pins! {
167-
FDCAN3 => (
168-
tx: [
169-
PA15<AF11>,
170-
PB4<AF11>,
171-
],
172-
rx: [
173-
PA8<AF11>,
174-
PB3<AF11>,
175-
])
176-
}
99+
impl Instance for FDCAN3 {}
177100

178-
impl Can<FDCAN3> {
179-
pub fn fdcan3(rb: FDCAN3) -> fdcan::FdCan<Self, fdcan::ConfigMode> {
180-
fdcan::FdCan::new(Self { rb }).into_config_mode()
181-
}
182-
}
183-
impl CanExt for FDCAN3 {
184-
fn fdcan_unchecked(self) -> fdcan::FdCan<Can<Self>, fdcan::ConfigMode> {
185-
Can::fdcan3(self)
186-
}
187-
}
188-
unsafe impl fdcan::Instance for Can<FDCAN3> {
189-
const REGISTERS: *mut fdcan::RegisterBlock = FDCAN3::ptr() as *mut _;
190-
}
191101
unsafe impl fdcan::message_ram::Instance for Can<FDCAN3> {
192102
const MSG_RAM: *mut message_ram::RegisterBlock = (0x4000_aaa0 as *mut _);
193103
}

‎src/lib.rs‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -107,15 +107,17 @@ impl<RB, const A: usize> Sealed for Periph<RB, A> {}
107107
pub trait Ptr: Sealed {
108108
/// RegisterBlock structure
109109
type RB;
110+
/// Pointer to the register block
111+
const PTR: *const Self::RB;
110112
/// Return the pointer to the register block
111-
fn ptr() -> *const Self::RB;
113+
fn ptr() -> *const Self::RB {
114+
Self::PTR
115+
}
112116
}
113117

114118
impl<RB, const A: usize> Ptr for Periph<RB, A> {
115119
type RB = RB;
116-
fn ptr() -> *const Self::RB {
117-
Self::ptr()
118-
}
120+
const PTR: *const Self::RB = Self::PTR;
119121
}
120122

121123
fn stripped_type_name<T>() -> &'static str {

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