instance

Author: burrbull

src/gpio/alt/g4.rs

@@ -787,6 +787,16 @@ pub mod lpuart1 {
             PG7<8>,
         ],
     }
+
+    use crate::pac::LPUART1 as UART;
+    impl SerialAsync for UART {
+        type Rx<Otype> = Rx<Otype>;
+        type Tx<Otype> = Tx<Otype>;
+    }
+    impl SerialFlowControl for UART {
+        type Cts = Cts;
+        type Rts = Rts;
+    }
 }
 
 #[cfg(any(feature = "gpio-g47x", feature = "gpio-g49x"))]

src/serial/usart.rs

@@ -86,6 +86,11 @@ impl Event {
     }
 }
 
+pub use gpio::alt::SerialAsync as CommonPins;
+
+// Implemented by all USART/UART instances
+pub trait Instance: crate::Sealed + crate::Ptr + Enable + Reset + CommonPins {}
+
 /// Serial receiver
 pub struct Rx<USART, Pin, Dma> {
     pin: Pin,
@@ -182,6 +187,8 @@ macro_rules! uart_shared {
             }
         )+
 
+        impl Instance for $USARTX {}
+
         impl<Pin, Dma> Rx<$USARTX, Pin, Dma> {
             /// Starts listening for an interrupt event
             pub fn listen(&mut self) {
@@ -579,41 +586,27 @@ macro_rules! uart_lp {
                 usart.cr3().reset();
 
                 usart.cr2().write(|w| unsafe {
-                    w.stop()
-                        .bits(config.stopbits.bits())
-                        .swap()
-                        .bit(config.swap)
+                    w.stop().bits(config.stopbits.bits());
+                    w.swap().bit(config.swap)
                 });
 
                 usart.cr3().write(|w| unsafe {
-                    w.txftcfg()
-                        .bits(config.tx_fifo_threshold.bits())
-                        .rxftcfg()
-                        .bits(config.rx_fifo_threshold.bits())
-                        .txftie()
-                        .bit(config.tx_fifo_interrupt)
-                        .rxftie()
-                        .bit(config.rx_fifo_interrupt)
+                    w.txftcfg().bits(config.tx_fifo_threshold.bits());
+                    w.rxftcfg().bits(config.rx_fifo_threshold.bits());
+                    w.txftie().bit(config.tx_fifo_interrupt);
+                    w.rxftie().bit(config.rx_fifo_interrupt)
                 });
 
                 // Enable the UART and perform remaining configuration.
                 usart.cr1().write(|w| {
-                    w.ue()
-                        .set_bit()
-                        .te()
-                        .set_bit()
-                        .re()
-                        .set_bit()
-                        .m0()
-                        .bit(config.wordlength == WordLength::DataBits9)
-                        .m1()
-                        .bit(config.wordlength == WordLength::DataBits7)
-                        .pce()
-                        .bit(config.parity != Parity::ParityNone)
-                        .ps()
-                        .bit(config.parity == Parity::ParityOdd)
-                        .fifoen()
-                        .bit(config.fifo_enable)
+                    w.ue().set_bit();
+                    w.te().set_bit();
+                    w.re().set_bit();
+                    w.m0().bit(config.wordlength == WordLength::DataBits9);
+                    w.m1().bit(config.wordlength == WordLength::DataBits7);
+                    w.pce().bit(config.parity != Parity::ParityNone);
+                    w.ps().bit(config.parity == Parity::ParityOdd);
+                    w.fifoen().bit(config.fifo_enable)
                 });
 
                 Ok(Serial {
@@ -726,10 +719,8 @@ macro_rules! uart_full {
                 usart.cr3().reset();
 
                 usart.cr2().write(|w| unsafe {
-                    w.stop()
-                        .bits(config.stopbits.bits())
-                        .swap()
-                        .bit(config.swap)
+                    w.stop().bits(config.stopbits.bits());
+                    w.swap().bit(config.swap)
                 });
 
                 if let Some(timeout) = config.receiver_timeout {
@@ -739,34 +730,22 @@ macro_rules! uart_full {
                 }
 
                 usart.cr3().write(|w| unsafe {
-                    w.txftcfg()
-                        .bits(config.tx_fifo_threshold.bits())
-                        .rxftcfg()
-                        .bits(config.rx_fifo_threshold.bits())
-                        .txftie()
-                        .bit(config.tx_fifo_interrupt)
-                        .rxftie()
-                        .bit(config.rx_fifo_interrupt)
+                    w.txftcfg().bits(config.tx_fifo_threshold.bits());
+                    w.rxftcfg().bits(config.rx_fifo_threshold.bits());
+                    w.txftie().bit(config.tx_fifo_interrupt);
+                    w.rxftie().bit(config.rx_fifo_interrupt)
                 });
 
                 // Enable the UART and perform remaining configuration.
                 usart.cr1().modify(|_, w| {
-                    w.ue()
-                        .set_bit()
-                        .te()
-                        .set_bit()
-                        .re()
-                        .set_bit()
-                        .m0()
-                        .bit(config.wordlength == WordLength::DataBits7)
-                        .m1()
-                        .bit(config.wordlength == WordLength::DataBits9)
-                        .pce()
-                        .bit(config.parity != Parity::ParityNone)
-                        .ps()
-                        .bit(config.parity == Parity::ParityOdd)
-                        .fifoen()
-                        .bit(config.fifo_enable)
+                    w.ue().set_bit();
+                    w.te().set_bit();
+                    w.re().set_bit();
+                    w.m0().bit(config.wordlength == WordLength::DataBits7);
+                    w.m1().bit(config.wordlength == WordLength::DataBits9);
+                    w.pce().bit(config.parity != Parity::ParityNone);
+                    w.ps().bit(config.parity == Parity::ParityOdd);
+                    w.fifoen().bit(config.fifo_enable)
                 });
 
                 Ok(Serial {