Oracle synthesis: verilog array format?

[gribeill]

I'm wondering if the Verilog oracle synthesis syntax supports vectors as inputs/outputs?

Minimal example:

Oracle declaration:

module oracle (a, b, c);
	input [1:0] a;
	input [1:0] b;
	output c;
        //random example function
	assign c = (a[0] & b[1]) ^ (a[1] & b[0]);
endmodule

With QASM:

OPENQASM 2.0;
include "qelib1.inc";

oracle test a, b, c { "reg_oracle.v" }

qreg a[2];
qreg b[2];
qreg c[1];

test a, b, c;

gives a compiler error:

test_oracle.qasm:10:10: Register c has incompatible length

Thanks!

[meamy]

Currently it can not. This is due to a limitation of the openQASM 2.0 language, which will (hopefully) be fixed in openQASM 3.0 (issue #323), where gates can only take individual qubits as parameters.

Thanks! Leaving this open as an enhancement for now, but if there are other missing features of Verilog that would be useful feel free to open up a separate feature request.