Since I have a bunch of fx2lp logic analyzers and a very good clock, I decided to profile them.
It turned out that the "boxed" ones (with written logic analyzer 24 mhz, are quite good (+/- 3 ppm).
The boards (which are based on the reference cypress devkit) instead are off by +96/+100 ppm.
nanoDLA have the exact same deviation of +100 ppm.
So I got curious and tried to understand the reason.
The reason traces back to Cypress. In their reference design the use 2 12 pF capacitors each on each leg of the 24 MHz crystal.
That values yield a 6pF capacitance which is way too little for the 24Mhz HC-49 crystals.
The solution(s):
The hardware solution:
Piggy back 2 22pF capacitors on top of the tiny SMD capacitors.
The software solution:
Set a -100 ppm correction in pulseview.
Caveat: perhaps it's my devices but I doubt that because of the Cypress devkit/reference error that you can see here:
https://community.element14.com/cfs-file/__key/communityserver-wikis-components-files/00-00-00-01-46/2275.Cypress.Schematics_5F00_1.zip
Note:
In most designs the capacitors are between 18 pF and 33 pF.
I don't know the exact value for these circuits but I "guess" that adding the 22 pF should slower down the crystal of about 100 ppm.
Digging it up a little more it turns out that the original design (with the 12 pF capacitors) was using a resonator and not a crystal!
Resonators have built-in load capacitors, the crystal does not.
Since I have a bunch of fx2lp logic analyzers and a very good clock, I decided to profile them.
It turned out that the "boxed" ones (with written logic analyzer 24 mhz, are quite good (+/- 3 ppm).
The boards (which are based on the reference cypress devkit) instead are off by +96/+100 ppm.
nanoDLA have the exact same deviation of +100 ppm.
So I got curious and tried to understand the reason.
The reason traces back to Cypress. In their reference design the use 2 12 pF capacitors each on each leg of the 24 MHz crystal.
That values yield a 6pF capacitance which is way too little for the 24Mhz HC-49 crystals.
The solution(s):
The hardware solution:
Piggy back 2 22pF capacitors on top of the tiny SMD capacitors.
The software solution:
Set a -100 ppm correction in pulseview.
Caveat: perhaps it's my devices but I doubt that because of the Cypress devkit/reference error that you can see here:
https://community.element14.com/cfs-file/__key/communityserver-wikis-components-files/00-00-00-01-46/2275.Cypress.Schematics_5F00_1.zip
Note:
In most designs the capacitors are between 18 pF and 33 pF.
I don't know the exact value for these circuits but I "guess" that adding the 22 pF should slower down the crystal of about 100 ppm.
Digging it up a little more it turns out that the original design (with the 12 pF capacitors) was using a resonator and not a crystal!
Resonators have built-in load capacitors, the crystal does not.