From 9a9db6d2b8728669182621084ac2e114c803598a Mon Sep 17 00:00:00 2001 From: beeman Date: Tue, 4 Nov 2025 17:34:16 -0800 Subject: [PATCH 1/2] fix typos, and add introduction to strc chapter --- src/smstrc.adoc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/smstrc.adoc b/src/smstrc.adoc index 00bd2fdc2..0c7bd55cf 100644 --- a/src/smstrc.adoc +++ b/src/smstrc.adoc @@ -1,5 +1,11 @@ == Self-hosted Trace ISA Extension (Smstrce1p0/Ssstrce1p0 and Smstrcn1p0/Ssstrcn1p0) +The Smstrce1p0/Ssstrce1p0 and Smstrcn1p0/Ssstrcn1p0 extensions introduce an ISA interface to the existing E-trace and N-trace (non-ISA) trace extensions, respectively. The intent is to simplify in-target software use of trace, also known as self-hosted trace, for debugging, performance analysis, fuzzing, code coverage, and other applications. + +The Smstrc*/Ssstrc* extensions depend upon Ssamb, as an asynchronous memory buffer is used as the trace sink. + +"Strc" refers to self-hosted trace, "e" vs "n" refer to E-trace vs N-trace, and "1p0" refers to version 1.0 of each trace extension. The machine-level extensions, Smstrc*, encompass all newly added registers and behavior modifications for a hart across all privilege levels. The corresponding supervisor-level extensions, Ssstrc*, are essentially identical to Smstrc*, except that they exclude machine-level registers and behaviors not intended to be directly accessible at the supervisor level. + [[strccsrs]] === CSRs @@ -96,11 +102,11 @@ The `sstrcctl` register provides supervisor mode access to a subset of `mstrcctl ==== Supervisor Self-hosted Trace Control and Status (`sstrcambcs`) -The `sstrcambcs` register is the Self-hosted trace instatiation of the `sambcs` register defined by the Ssamb extension, see <>. See <> for Self-hosted trace memory buffer details. +The `sstrcambcs` register is the Self-hosted trace instantiation of the `sambcs` register defined by the Ssamb extension, see <>. See <> for Self-hosted trace memory buffer details. ==== Supervisor Self-hosted Trace AMB Address (`sstrcambaddr`) -The `sstrcambaddr` register is the Self-hosted trace instatiation of the `sambaddr` register defined in the Ssamb specification, see <>. See <> for Self-hosted trace Memory Buffer details. +The `sstrcambaddr` register is the Self-hosted trace instantiation of the `sambaddr` register defined in the Ssamb specification, see <>. See <> for Self-hosted trace Memory Buffer details. ==== Supervisor Context Register (`scontext`) From 6b612cec09c47512d0c3b9de3e075b5528edca5e Mon Sep 17 00:00:00 2001 From: beeman Date: Tue, 4 Nov 2025 17:45:53 -0800 Subject: [PATCH 2/2] update f0s_width value to support all modes --- src/smstrc.adoc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/smstrc.adoc b/src/smstrc.adoc index 0c7bd55cf..488cb2539 100644 --- a/src/smstrc.adoc +++ b/src/smstrc.adoc @@ -241,10 +241,10 @@ indicates that there is no jump target cache implemented. |_ctype_width_p_ | 2 (precise) | Width of the *ctype* bus. |_context_width_p_ | 64 bits | Width of *context* bus. |_time_width_p_ | Implementation-defined | Width of *time* bus -|_ecause_width_p_ | 7 (Interrupt bit + 0..63 cause values) | Width of *exception cause* bus +|_ecause_width_p_ | 6 (0..63 cause values) | Width of *exception cause* bus |_ecause_choice_p_ | Any | Number of bits of exception cause to match using multiple choice -|_f0s_width_p_ | 1, or 2 if want room for growth? | Width of the *subformat* field in format 0 _te_inst_ packets. +|_f0s_width_p_ | 2 | Width of the *subformat* field in format 0 _te_inst_ packets. |_filter_context_p_ | Any | Filtering on context supported when 1 |_filter_time_p_ | Any | Filtering on time supported when 1 |_filter_excint_p_ | Any | Filtering on exception cause or interrupt