diff --git a/backends/instructions_appendix/all_instructions.golden.adoc b/backends/instructions_appendix/all_instructions.golden.adoc
index 46a78c77d..dfb86f725 100644
--- a/backends/instructions_appendix/all_instructions.golden.adoc
+++ b/backends/instructions_appendix/all_instructions.golden.adoc
@@ -1,6 +1,6 @@
 = Instruction Appendix
 :doctype: book
-:wavedrom: /workspace/riscv-unified-db/node_modules/.bin/wavedrom-cli
+:wavedrom: /workspaces/riscv-unified-db/node_modules/.bin/wavedrom-cli
 // Now the document header is complete and the wavedrom attribute is active.
 
 
@@ -16539,6 +16539,126 @@ Included in::
 |===
 
 
+[#udb:doc:inst:prefetch_i]
+== prefetch.i
+
+Synopsis::
+Cache block prefetch for instruction fetch
+
+Assembly::
+prefetch.i imm(xs1)
+
+Encoding::
+[wavedrom, ,svg,subs='attributes',width="100%"]
+....
+{"reg":[{"bits":15,"name": 0x6013,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":5,"name": 0x0,"type":2},{"bits":7,"name": "imm","type":4}]}
+....
+
+Description::
+A prefetch.i instruction indicates to hardware that the cache block whose
+effective address is the sum of the base address specified in rs1 and the
+sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000,
+is likely to be accessed by an instruction fetch in the near future.
+
+
+Decode Variables::
+[width="100%", cols="1,2", options="header"]
+|===
+|Variable Name |Location
+|imm |$encoding[31:25]
+|xs1 |$encoding[19:15]
+|===
+
+Included in::
+[options="autowrap,autowidth"]
+|===
+| Extension | Version
+
+| *Zicbop* | ~> 1.0.0
+
+|===
+
+
+[#udb:doc:inst:prefetch_r]
+== prefetch.r
+
+Synopsis::
+Cache block prefetch for data read
+
+Assembly::
+prefetch.r imm(xs1)
+
+Encoding::
+[wavedrom, ,svg,subs='attributes',width="100%"]
+....
+{"reg":[{"bits":15,"name": 0x6013,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":5,"name": 0x1,"type":2},{"bits":7,"name": "imm","type":4}]}
+....
+
+Description::
+A prefetch.r instruction indicates to hardware that the cache block whose
+effective address is the sum of the base address specified in rs1 and the
+sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000,
+is likely to be accessed by a data read (i.e. load) in the near future.
+
+
+Decode Variables::
+[width="100%", cols="1,2", options="header"]
+|===
+|Variable Name |Location
+|imm |$encoding[31:25]
+|xs1 |$encoding[19:15]
+|===
+
+Included in::
+[options="autowrap,autowidth"]
+|===
+| Extension | Version
+
+| *Zicbop* | ~> 1.0.0
+
+|===
+
+
+[#udb:doc:inst:prefetch_w]
+== prefetch.w
+
+Synopsis::
+Cache block prefetch for data write
+
+Assembly::
+prefetch.w imm(xs1)
+
+Encoding::
+[wavedrom, ,svg,subs='attributes',width="100%"]
+....
+{"reg":[{"bits":15,"name": 0x6013,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":5,"name": 0x3,"type":2},{"bits":7,"name": "imm","type":4}]}
+....
+
+Description::
+A prefetch.w instruction indicates to hardware that the cache block whose
+effective address is the sum of the base address specified in rs1 and the
+sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000,
+is likely to be accessed by a data write (i.e. store) in the near future.
+
+
+Decode Variables::
+[width="100%", cols="1,2", options="header"]
+|===
+|Variable Name |Location
+|imm |$encoding[31:25]
+|xs1 |$encoding[19:15]
+|===
+
+Included in::
+[options="autowrap,autowidth"]
+|===
+| Extension | Version
+
+| *Zicbop* | ~> 1.0.0
+
+|===
+
+
 [#udb:doc:inst:rem]
 == rem
 
diff --git a/spec/std/isa/inst/I/ori.yaml b/spec/std/isa/inst/I/ori.yaml
index 46ff34e8b..85fb173f3 100644
--- a/spec/std/isa/inst/I/ori.yaml
+++ b/spec/std/isa/inst/I/ori.yaml
@@ -25,32 +25,12 @@ access:
   vs: always
   vu: always
 data_independent_timing: true
+hints:
+  - { $ref: inst/Zicbop/prefetch.r.yaml# }
+  - { $ref: inst/Zicbop/prefetch.w.yaml# }
+  - { $ref: inst/Zicbop/prefetch.i.yaml# }
 operation(): |
-  if (implemented?(ExtensionName::Zicbop)) {
-    if (xd == 0) {
-      if (imm[4:0] == 0) {
-        # prefetch.i instruction
-        Bits<12> offset = {imm[11:5], xd};
-        prefetch_instruction(offset);
-      } else if (imm[4:0] == 1) {
-        # prefetch.r instruction
-        Bits<12> offset = {imm[11:5], xd};
-        prefetch_read(offset);
-      } else if (imm[4:0] == 3) {
-        # prefetch.r instruction
-        Bits<12> offset = {imm[11:5], xd};
-        prefetch_write(offset);
-      }
-    }
-  }
   X[xd] = X[xs1] | $signed(imm);
-pseudoinstructions:
-  - when: (xd == 0) && (imm[4:0] == 0)
-    to: prefetch.i offset
-  - when: (xd == 0) && (imm[4:0] == 1)
-    to: prefetch.r offset
-  - when: (xd == 0) && (imm[4:0] == 3)
-    to: prefetch.w offset
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
diff --git a/spec/std/isa/inst/Zicbop/prefetch.i.yaml b/spec/std/isa/inst/Zicbop/prefetch.i.yaml
new file mode 100644
index 000000000..8abecddf4
--- /dev/null
+++ b/spec/std/isa/inst/Zicbop/prefetch.i.yaml
@@ -0,0 +1,32 @@
+# Copyright (c) Jordan Carlin
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: prefetch.i
+long_name: Cache block prefetch for instruction fetch
+description: |
+  A prefetch.i instruction indicates to hardware that the cache block whose
+  effective address is the sum of the base address specified in rs1 and the
+  sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000,
+  is likely to be accessed by an instruction fetch in the near future.
+definedBy: Zicbop
+assembly: imm(xs1)
+encoding:
+  match: -------00000-----110000000010011
+  variables:
+    - name: imm
+      location: 31-25
+    - name: xs1
+      location: 19-15
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |
+  XReg address = X[xs1] + $signed(imm << 5);
+  prefetch_instruction(address);
diff --git a/spec/std/isa/inst/Zicbop/prefetch.r.yaml b/spec/std/isa/inst/Zicbop/prefetch.r.yaml
new file mode 100644
index 000000000..80b28e694
--- /dev/null
+++ b/spec/std/isa/inst/Zicbop/prefetch.r.yaml
@@ -0,0 +1,32 @@
+# Copyright (c) Jordan Carlin
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: prefetch.r
+long_name: Cache block prefetch for data read
+description: |
+  A prefetch.r instruction indicates to hardware that the cache block whose
+  effective address is the sum of the base address specified in rs1 and the
+  sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000,
+  is likely to be accessed by a data read (i.e. load) in the near future.
+definedBy: Zicbop
+assembly: imm(xs1)
+encoding:
+  match: -------00001-----110000000010011
+  variables:
+    - name: imm
+      location: 31-25
+    - name: xs1
+      location: 19-15
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |
+  XReg address = X[xs1] + $signed(imm << 5);
+  prefetch_read(address);
diff --git a/spec/std/isa/inst/Zicbop/prefetch.w.yaml b/spec/std/isa/inst/Zicbop/prefetch.w.yaml
new file mode 100644
index 000000000..44cdaa693
--- /dev/null
+++ b/spec/std/isa/inst/Zicbop/prefetch.w.yaml
@@ -0,0 +1,32 @@
+# Copyright (c) Jordan Carlin
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: prefetch.w
+long_name: Cache block prefetch for data write
+description: |
+  A prefetch.w instruction indicates to hardware that the cache block whose
+  effective address is the sum of the base address specified in rs1 and the
+  sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000,
+  is likely to be accessed by a data write (i.e. store) in the near future.
+definedBy: Zicbop
+assembly: imm(xs1)
+encoding:
+  match: -------00011-----110000000010011
+  variables:
+    - name: imm
+      location: 31-25
+    - name: xs1
+      location: 19-15
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |
+  XReg address = X[xs1] + $signed(imm << 5);
+  prefetch_write(address);