Expand maybe ops to individual instruction yaml files

[jordancarlin]

The mop.r.n, mop.rr.n, and c.mop.n instruction families are each defined in the database as a single instruction/yaml with pseudoinstructions for the specific instructions (mop.r.1, mop.r.2, etc.). Each of these are individual instructions and should therefore have their own yaml files. This should probably be done using a layout file.

The current approach means that only a single version of the instruction appears in generated artifacts (like the SystemVerilog header in #1090). The riscv-opcodes version of the SystemVerilog header includes encodings for all of the individual instructions along with a more general encoding for each family of instructions.