Some Issues Need to be Fixed

[kazutoiris]

Issues to be Fixed

1. Handling of the WARP type in burst of AXI4 protocol is missing.
   https://github.com/oscc-ip/sram/blob/c73ed0c37e9a87ab0e62f007589dc583b5697c04/rtl/axi4_sram_fsm.sv#L172-L173
   https://github.com/oscc-ip/sram/blob/c73ed0c37e9a87ab0e62f007589dc583b5697c04/rtl/axi4_sram_fsm.sv#L195-L196

2. sram.bm_i and axi4.wstrb have the same polarity, but here it's inverted.
   https://github.com/oscc-ip/sram/blob/c73ed0c37e9a87ab0e62f007589dc583b5697c04/rtl/mem_ctrl.sv#L57

Recommendations for Improvement

1. Using #1 for delay is unnecessary as it doesn't take effect during synthesis.
   https://github.com/oscc-ip/sram/blob/c73ed0c37e9a87ab0e62f007589dc583b5697c04/rtl/axi4_sram_fsm.sv#L227-L230

2. Retrieving address in the ar channel and transferring data in the r channel can be performed simultaneously. It's recommended to use pipeline instead of state machine, which will improve bandwidth.