From 8c7e3cb028f53882c55208e02fdb34bccf7b95e4 Mon Sep 17 00:00:00 2001
From: haowhsu-quic <quic_haowhsu@quicinc.com>
Date: Wed, 29 Oct 2025 13:36:04 +0800
Subject: [PATCH] Qualcomm AI Engine Direct - supprot SAR2230P

- add soc SAR2230P
---
 backends/qualcomm/README.md                          | 1 +
 backends/qualcomm/serialization/qc_compiler_spec.fbs | 2 ++
 backends/qualcomm/serialization/qc_schema.py         | 3 +++
 backends/qualcomm/utils/utils.py                     | 2 ++
 4 files changed, 8 insertions(+)

diff --git a/backends/qualcomm/README.md b/backends/qualcomm/README.md
index faff5786b8b..89c7cf07b25 100644
--- a/backends/qualcomm/README.md
+++ b/backends/qualcomm/README.md
@@ -28,6 +28,7 @@ Please check `generate_qnn_executorch_compiler_spec()` in
 - SXR2230P
 - SXR2330P
 - QCS9100
+- SAR2230P
 
 ### Adding more supported Chipset
 Currently, users cannot add additional chipset models because the chipset ID is not accessible to community users. If you have specific chipset models you wish to add, please contact one of the authors in the `Code Reviews` section at the bottom of this page.
diff --git a/backends/qualcomm/serialization/qc_compiler_spec.fbs b/backends/qualcomm/serialization/qc_compiler_spec.fbs
index 145ae0010fc..3000c9e1187 100644
--- a/backends/qualcomm/serialization/qc_compiler_spec.fbs
+++ b/backends/qualcomm/serialization/qc_compiler_spec.fbs
@@ -18,6 +18,7 @@ enum HtpArch: int {
   V73 = 73,
   V75 = 75,
   V79 = 79,
+  V81 = 81,
 }
 
 table HtpInfo {
@@ -44,6 +45,7 @@ enum QcomChipset: int {
   SXR2230P = 53,
   SXR2330P = 75,
   QCS9100 = 77,
+  SAR2230P = 95,
 }
 
 /// Indicate the information of the specified SoC.
diff --git a/backends/qualcomm/serialization/qc_schema.py b/backends/qualcomm/serialization/qc_schema.py
index 9f4b37c13d1..bcbd53a235e 100644
--- a/backends/qualcomm/serialization/qc_schema.py
+++ b/backends/qualcomm/serialization/qc_schema.py
@@ -27,6 +27,7 @@ class HtpArch(IntEnum):
     V73 = 73
     V75 = 75
     V79 = 79
+    V81 = 81
 
 
 @dataclass
@@ -50,6 +51,7 @@ class QcomChipset(IntEnum):
     SXR2230P = 53  # v69
     SXR2330P = 75  # v79
     QCS9100 = 77  # v73
+    SAR2230P = 95  # v81
 
 
 @dataclass
@@ -71,6 +73,7 @@ class SocInfo:
     QcomChipset.SXR2230P: SocInfo(QcomChipset.SXR2230P, HtpInfo(HtpArch.V69, 8)),
     QcomChipset.SXR2330P: SocInfo(QcomChipset.SXR2330P, HtpInfo(HtpArch.V79, 8)),
     QcomChipset.QCS9100: SocInfo(QcomChipset.QCS9100, HtpInfo(HtpArch.V73, 8)),
+    QcomChipset.SAR2230P: SocInfo(QcomChipset.SAR2230P, HtpInfo(HtpArch.V81, 4)),
 }
 
 
diff --git a/backends/qualcomm/utils/utils.py b/backends/qualcomm/utils/utils.py
index 91610301515..d26e9530f0b 100644
--- a/backends/qualcomm/utils/utils.py
+++ b/backends/qualcomm/utils/utils.py
@@ -1100,6 +1100,7 @@ def get_soc_to_arch_map():
         "SXR2230P": HtpArch.V69,
         "SXR2330P": HtpArch.V79,
         "QCS9100": HtpArch.V73,
+        "SAR2230P": HtpArch.V81,
     }
 
 
@@ -1117,6 +1118,7 @@ def get_soc_to_chipset_map():
         "SXR2230P": QcomChipset.SXR2230P,
         "SXR2330P": QcomChipset.SXR2330P,
         "QCS9100": QcomChipset.QCS9100,
+        "SAR2230P": QcomChipset.SAR2230P,
     }