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Remove redundant assignment in clk_int_div.sv
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src/clk_int_div.sv

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@@ -134,7 +134,6 @@ module clk_int_div #(
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toggle_ffs_en = 1'b1;
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gate_en_d = 1'b0;
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clk_gate_state_d = clk_gate_state_q;
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case (clk_gate_state_q)
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IDLE: begin
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gate_en_d = 1'b1;

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