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build: support rv64im zkVM target via lower-atomic pass
addresses #4
1 parent 6e55612 commit aadb22b

4 files changed

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.github/workflows/ci.yml

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@@ -55,16 +55,16 @@ jobs:
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run: ./scripts/run_ef_tests.sh ${{ matrix.trie }}
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no-std:
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name: no_std (RISC-V)
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name: no_std (RISC-V rv64im)
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runs-on: ubuntu-latest
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timeout-minutes: 30
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steps:
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- uses: actions/checkout@v4
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- uses: dtolnay/rust-toolchain@stable
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- uses: dtolnay/rust-toolchain@nightly
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with:
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targets: riscv32imac-unknown-none-elf
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components: rust-src
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- uses: Swatinem/rust-cache@v2
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with:
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cache-on-failure: true
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- name: Build stateless for riscv32imac
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- name: Build stateless for riscv64im
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run: ./scripts/check_no_std.sh

README.md

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@@ -44,7 +44,11 @@ let block_access_list = validation.block_access_list;
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## `no_std`
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The `stateless` crate is `#![no_std]` compatible and builds for RISC-V targets (`riscv32imac-unknown-none-elf`), making it suitable for use in zkVM environments.
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The `stateless` crate is `#![no_std]` compatible and builds for the 64-bit RISC-V target
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(`riscv64im-unknown-none-elf`), making it suitable for use in zkVM environments.
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> **Note:** The build temporarily relies on the LLVM `lower-atomic` pass
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> to lower atomic instructions into non-atomic equivalents.
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## Running EF tests
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scripts/check_no_std.sh

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#!/usr/bin/env bash
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set -eo pipefail
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target=riscv32imac-unknown-none-elf
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target=targets/riscv64im-unknown-none-elf.json
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cmd=(cargo +stable build --no-default-features --target "$target" -p stateless)
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export RUSTFLAGS="-C passes=lower-atomic"
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cmd=(
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cargo +nightly build
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--no-default-features
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--target "$target"
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-Zbuild-std=core,alloc
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-p stateless
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)
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echo "Running: ${cmd[*]}"
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"${cmd[@]}"
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{
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"arch": "riscv64",
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"code-model": "medium",
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"cpu": "generic-rv64",
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"crt-objects-fallback": "false",
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"data-layout": "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128",
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"eh-frame-header": false,
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"emit-debug-gdb-scripts": false,
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"features": "+m",
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"linker": "rust-lld",
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"linker-flavor": "gnu-lld",
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"llvm-abiname": "lp64",
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"llvm-target": "riscv64-unknown-none-elf",
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"max-atomic-width": 64,
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"metadata": {
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"description": "Bare RISC-V (RV64IM ISA)",
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"host_tools": false,
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"std": false,
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"tier": 2
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},
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"os": "none",
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"panic-strategy": "abort",
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"relocation-model": "static",
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"supported-sanitizers": [
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"shadow-call-stack",
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"kernel-address"
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],
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"target-pointer-width": 64
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}

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