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JeanRochCoulonASintzoff
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Flist, ariane_wrapper.sv: add wrapper to expand rvfi and axi structures
needed for dc_shell Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
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‎core/Flist.cv32a6_imac_sv0‎

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@@ -46,6 +46,7 @@ ${CVA6_REPO_DIR}/corev_apu/tb/ariane_soc_pkg.sv
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// TODO: ariane_axi_pkg is dependent on this.
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${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
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${CVA6_REPO_DIR}/corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv
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${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
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// Packages
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${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv
@@ -86,6 +87,7 @@ ${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
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// Top-level source files (not necessarily instantiated at the top of the cva6).
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${CVA6_REPO_DIR}/core/ariane_wrapper.sv
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${CVA6_REPO_DIR}/core/ariane.sv
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${CVA6_REPO_DIR}/core/alu.sv
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// Note: depends on fpnew_pkg, above

‎core/Flist.cv64a6_imacfd_sv39‎

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@@ -46,6 +46,7 @@ ${CVA6_REPO_DIR}/corev_apu/tb/ariane_soc_pkg.sv
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// TODO: ariane_axi_pkg is dependent on this.
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${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
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${CVA6_REPO_DIR}/corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv
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${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
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// Packages
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${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv
@@ -86,6 +87,7 @@ ${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
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// Top-level source files (not necessarily instantiated at the top of the cva6).
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${CVA6_REPO_DIR}/core/ariane_wrapper.sv
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${CVA6_REPO_DIR}/core/ariane.sv
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${CVA6_REPO_DIR}/core/alu.sv
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// Note: depends on fpnew_pkg, above

‎core/ariane_wrapper.sv‎

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// Copyright 2021 Thales DIS design services SAS
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//
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// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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// You may obtain a copy of the License at https://solderpad.org/licenses/
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//
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// Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
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module ariane_wrapper import ariane_pkg::*; #(
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parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
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) (
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input logic clk_i,
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input logic rst_ni,
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// Core ID, Cluster ID and boot address are considered more or less static
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input logic [63:0] boot_addr_i, // reset boot address
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input logic [63:0] hart_id_i, // hart id in a multicore environment (reflected in a CSR)
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// Interrupt inputs
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input logic [1:0] irq_i, // level sensitive IR lines, mip & sip (async)
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input logic ipi_i, // inter-processor interrupts (async)
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// Timer facilities
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input logic time_irq_i, // timer interrupt in (async)
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input logic debug_req_i, // debug request (async)
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`ifdef FIRESIM_TRACE
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// firesim trace port
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output traced_instr_pkg::trace_port_t trace_o,
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`endif
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// RISC-V formal interface port (`rvfi`):
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// Can be left open when formal tracing is not needed.
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output logic rvfi_valid_1,
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output logic[63:0] rvfi_order_1,
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output logic[31:0] rvfi_insn_1,
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output logic rvfi_trap_1,
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output logic rvfi_halt_1,
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output logic rvfi_intr_1,
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output logic[2:0] rvfi_mode_1,
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output logic[2:0] rvfi_ixl_1,
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output logic[4:0] rvfi_rs1_addr_1,
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output logic[4:0] rvfi_rs2_addr_1,
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output logic[riscv::XLEN-1:0] rvfi_rs1_rdata_1,
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output logic[riscv::XLEN-1:0] rvfi_rs2_rdata_1,
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output logic[4:0] rvfi_rd_addr_1,
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output logic[riscv::XLEN-1:0] rvfi_rd_wdata_1,
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output logic[riscv::XLEN-1:0] rvfi_pc_rdata_1,
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output logic[riscv::XLEN-1:0] rvfi_pc_wdata_1,
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output logic[riscv::XLEN-1:0] rvfi_mem_addr_1,
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output logic[(riscv::XLEN)/8-1:0] rvfi_mem_rmask_1,
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output logic[(riscv::XLEN)/8-1:0] rvfi_mem_wmask_1,
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output logic[riscv::XLEN-1:0] rvfi_mem_rdata_1,
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output logic[riscv::XLEN-1:0] rvfi_mem_wdata_1,
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output logic rvfi_valid_0,
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output logic[63:0] rvfi_order_0,
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output logic[31:0] rvfi_insn_0,
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output logic rvfi_trap_0,
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output logic rvfi_halt_0,
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output logic rvfi_intr_0,
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output logic[2:0] rvfi_mode_0,
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output logic[2:0] rvfi_ixl_0,
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output logic[4:0] rvfi_rs1_addr_0,
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output logic[4:0] rvfi_rs2_addr_0,
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output logic[riscv::XLEN-1:0] rvfi_rs1_rdata_0,
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output logic[riscv::XLEN-1:0] rvfi_rs2_rdata_0,
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output logic[4:0] rvfi_rd_addr_0,
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output logic[riscv::XLEN-1:0] rvfi_rd_wdata_0,
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output logic[riscv::XLEN-1:0] rvfi_pc_rdata_0,
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output logic[riscv::XLEN-1:0] rvfi_pc_wdata_0,
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output logic[riscv::XLEN-1:0] rvfi_mem_addr_0,
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output logic[(riscv::XLEN)/8-1:0] rvfi_mem_rmask_0,
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output logic[(riscv::XLEN)/8-1:0] rvfi_mem_wmask_0,
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output logic[riscv::XLEN-1:0] rvfi_mem_rdata_0,
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output logic[riscv::XLEN-1:0] rvfi_mem_wdata_0,
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`ifdef PITON_ARIANE
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// L15 (memory side)
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output wt_cache_pkg::l15_req_t l15_req_o,
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input wt_cache_pkg::l15_rtrn_t l15_rtrn_i
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`else
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// memory side, AXI Master
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output ariane_axi::id_t aw_id_o,
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output ariane_axi::addr_t aw_addr_o,
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output axi_pkg::len_t aw_len_o,
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output axi_pkg::size_t aw_size_o,
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output axi_pkg::burst_t aw_burst_o,
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output logic aw_lock_o,
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output axi_pkg::cache_t aw_cache_o,
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output axi_pkg::prot_t aw_prot_o,
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output axi_pkg::qos_t aw_qos_o,
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output axi_pkg::region_t aw_region_o,
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output axi_pkg::atop_t aw_atop_o,
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output ariane_axi::user_t aw_user_o,
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output logic aw_valid_o,
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output ariane_axi::data_t w_data_o,
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output ariane_axi::strb_t w_strb_o,
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output logic w_last_o,
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output ariane_axi::user_t w_user_o,
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output logic w_valid_o,
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output logic b_ready_o,
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output ariane_axi::id_t ar_id_o,
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output ariane_axi::addr_t ar_addr_o,
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output axi_pkg::len_t ar_len_o,
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output axi_pkg::size_t ar_size_o,
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output axi_pkg::burst_t ar_burst_o,
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output logic ar_lock_o,
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output axi_pkg::cache_t ar_cache_o,
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output axi_pkg::prot_t ar_prot_o,
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output axi_pkg::qos_t ar_qos_o,
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output axi_pkg::region_t ar_region_o,
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output ariane_axi::user_t ar_user_o,
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output logic ar_valid_o,
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output logic r_ready_o,
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input logic aw_ready_i,
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input logic ar_ready_i,
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input logic w_ready_i,
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input logic b_valid_i,
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input ariane_axi::id_t b_id_i,
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input axi_pkg::resp_t b_resp_i,
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input ariane_axi::user_t b_user_i,
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input logic r_valid_i,
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input ariane_axi::id_t r_id_i,
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input ariane_axi::data_t r_data_i,
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input axi_pkg::resp_t r_resp_i,
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input logic r_last_i,
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input ariane_axi::user_t r_user_i
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`endif
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);
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ariane_axi::req_t axi_ariane_req;
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ariane_axi::resp_t axi_ariane_resp;
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ariane_rvfi_pkg::rvfi_port_t rvfi;
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assign aw_id_o = axi_ariane_req.aw.id;
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assign aw_addr_o = axi_ariane_req.aw.addr;
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assign aw_len_o = axi_ariane_req.aw.len;
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assign aw_size_o = axi_ariane_req.aw.size;
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assign aw_burst_o = axi_ariane_req.aw.burst;
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assign aw_lock_o = axi_ariane_req.aw.lock;
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assign aw_cache_o = axi_ariane_req.aw.cache;
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assign aw_prot_o = axi_ariane_req.aw.prot;
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assign aw_qos_o = axi_ariane_req.aw.qos;
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assign aw_region_o = axi_ariane_req.aw.region;
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assign aw_atop_o = axi_ariane_req.aw.atop;
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assign aw_user_o = axi_ariane_req.aw.user;
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assign aw_valid_o = axi_ariane_req.aw_valid;
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assign w_data_o = axi_ariane_req.w.data;
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assign w_strb_o = axi_ariane_req.w.strb;
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assign w_last_o = axi_ariane_req.w.last;
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assign w_user_o = axi_ariane_req.w.user;
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assign w_valid_o = axi_ariane_req.w_valid;
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assign b_ready_o = axi_ariane_req.b_ready;
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assign ar_id_o = axi_ariane_req.ar.id;
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assign ar_addr_o = axi_ariane_req.ar.addr;
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assign ar_len_o = axi_ariane_req.ar.len;
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assign ar_size_o = axi_ariane_req.ar.size;
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assign ar_burst_o = axi_ariane_req.ar.burst;
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assign ar_lock_o = axi_ariane_req.ar.lock;
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assign ar_cache_o = axi_ariane_req.ar.cache;
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assign ar_prot_o = axi_ariane_req.ar.prot;
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assign ar_qos_o = axi_ariane_req.ar.qos;
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assign ar_region_o = axi_ariane_req.ar.region;
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assign ar_user_o = axi_ariane_req.ar.user;
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assign ar_valid_o = axi_ariane_req.ar_valid;
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assign r_ready_o = axi_ariane_req.r_ready;
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assign axi_ariane_resp.aw_ready = aw_ready_i;
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assign axi_ariane_resp.ar_ready = ar_ready_i;
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assign axi_ariane_resp.w_ready = w_ready_i;
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assign axi_ariane_resp.b_valid = b_valid_i;
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assign axi_ariane_resp.b.id = b_id_i;
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assign axi_ariane_resp.b.resp = b_resp_i;
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assign axi_ariane_resp.b.user = b_user_i;
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assign axi_ariane_resp.r_valid = r_valid_i;
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assign axi_ariane_resp.r.id = r_id_i;
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assign axi_ariane_resp.r.data = r_data_i;
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assign axi_ariane_resp.r.resp = r_resp_i;
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assign axi_ariane_resp.r.last = r_last_i;
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assign axi_ariane_resp.r.user = r_user_i;
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assign rvfi_valid_1 = rvfi[1].valid;
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assign rvfi_order_1 = rvfi[1].order;
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assign rvfi_insn_1 = rvfi[1].insn;
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assign rvfi_trap_1 = rvfi[1].trap;
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assign rvfi_halt_1 = rvfi[1].halt;
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assign rvfi_intr_1 = rvfi[1].intr;
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assign rvfi_mode_1 = rvfi[1].mode;
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assign rvfi_ixl_1 = rvfi[1].ixl;
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assign rvfi_rs1_addr_1 = rvfi[1].rs1_addr;
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assign rvfi_rs2_addr_1 = rvfi[1].rs2_addr;
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assign rvfi_rs1_rdata_1 = rvfi[1].rs1_rdata;
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assign rvfi_rs2_rdata_1 = rvfi[1].rs2_rdata;
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assign rvfi_rd_addr_1 = rvfi[1].rd_addr;
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assign rvfi_rd_wdata_1 = rvfi[1].rd_wdata;
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assign rvfi_pc_rdata_1 = rvfi[1].pc_rdata;
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assign rvfi_pc_wdata_1 = rvfi[1].pc_wdata;
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assign rvfi_mem_addr_1 = rvfi[1].mem_addr;
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assign rvfi_mem_rmask_1 = rvfi[1].mem_rmask;
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assign rvfi_mem_wmask_1 = rvfi[1].mem_wmask;
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assign rvfi_mem_rdata_1 = rvfi[1].mem_rdata;
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assign rvfi_mem_wdata_1 = rvfi[1].mem_wdata;
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assign rvfi_valid_0 = rvfi[0].valid;
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assign rvfi_order_0 = rvfi[0].order;
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assign rvfi_insn_0 = rvfi[0].insn;
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assign rvfi_trap_0 = rvfi[0].trap;
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assign rvfi_halt_0 = rvfi[0].halt;
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assign rvfi_intr_0 = rvfi[0].intr;
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assign rvfi_mode_0 = rvfi[0].mode;
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assign rvfi_ixl_0 = rvfi[0].ixl;
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assign rvfi_rs1_addr_0 = rvfi[0].rs1_addr;
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assign rvfi_rs2_addr_0 = rvfi[0].rs2_addr;
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assign rvfi_rs1_rdata_0 = rvfi[0].rs1_rdata;
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assign rvfi_rs2_rdata_0 = rvfi[0].rs2_rdata;
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assign rvfi_rd_addr_0 = rvfi[0].rd_addr;
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assign rvfi_rd_wdata_0 = rvfi[0].rd_wdata;
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assign rvfi_pc_rdata_0 = rvfi[0].pc_rdata;
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assign rvfi_pc_wdata_0 = rvfi[0].pc_wdata;
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assign rvfi_mem_addr_0 = rvfi[0].mem_addr;
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assign rvfi_mem_rmask_0 = rvfi[0].mem_rmask;
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assign rvfi_mem_wmask_0 = rvfi[0].mem_wmask;
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assign rvfi_mem_rdata_0 = rvfi[0].mem_rdata;
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assign rvfi_mem_wdata_0 = rvfi[0].mem_wdata;
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ariane #(
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.ArianeCfg ( ariane_soc::ArianeSocCfg )
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) i_ariane (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.boot_addr_i ( boot_addr_i ),
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.hart_id_i ( hart_id_i ),
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.irq_i ( irq_i ),
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.ipi_i ( ipi_i ),
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.time_irq_i ( time_irq_i ),
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.rvfi_o ( rvfi ),
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.debug_req_i ( debug_req_i ),
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.axi_req_o ( axi_ariane_req ),
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.axi_resp_i ( axi_ariane_resp )
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);
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endmodule // ariane_wrapper

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