UART Design and Implementation on BASYS 3 Board Using SystemVerilog You can run the project using Xilinx Vivado. The source files and the constraints are inside the folder CS_223_Project_Full. Generate bitstream and load the bitstream into two BASYS 3 boards, and connect the two boards via jumper cables, keeping in mind the connection ports specified in the constraints file. You can connect a board to itself as well.