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[ot] hw/riscv: ot_earlgrey: add jtag support to lc ctrl
Signed-off-by: Luís Marques <[email protected]>
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‎hw/riscv/ot_earlgrey.c‎

Lines changed: 99 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -38,13 +38,15 @@
3838
#include "hw/jtag/tap_ctrl.h"
3939
#include "hw/jtag/tap_ctrl_rbb.h"
4040
#include "hw/misc/pulp_rv_dm.h"
41+
#include "hw/opentitan/ot_address_space.h"
4142
#include "hw/opentitan/ot_aes.h"
4243
#include "hw/opentitan/ot_alert.h"
4344
#include "hw/opentitan/ot_aon_timer.h"
4445
#include "hw/opentitan/ot_ast_eg.h"
4546
#include "hw/opentitan/ot_clkmgr.h"
4647
#include "hw/opentitan/ot_common.h"
4748
#include "hw/opentitan/ot_csrng.h"
49+
#include "hw/opentitan/ot_dm_tl.h"
4850
#include "hw/opentitan/ot_edn.h"
4951
#include "hw/opentitan/ot_entropy_src.h"
5052
#include "hw/opentitan/ot_flash.h"
@@ -100,6 +102,8 @@ static void ot_eg_soc_otp_ctrl_configure(
100102
DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent);
101103
static void ot_eg_soc_tap_ctrl_configure(
102104
DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent);
105+
static void ot_eg_soc_lc_ctrl_tap_ctrl_configure(
106+
DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent);
103107
static void ot_eg_soc_spi_device_configure(
104108
DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent);
105109
static void ot_eg_soc_uart_configure(DeviceState *dev, const IbexDeviceDef *def,
@@ -111,6 +115,14 @@ static void ot_eg_soc_usbdev_configure(
111115
/* Constants */
112116
/* ------------------------------------------------------------------------ */
113117

118+
enum OtEgMemoryRegion {
119+
OT_EG_DEFAULT_MEMORY_REGION,
120+
OT_EG_LC_CTRL_TAP_MEMORY_REGION,
121+
};
122+
123+
#define LC_CTRL_TAP_MEMORY(_addr_) \
124+
IBEX_MEMMAP_MAKE_REG((_addr_), OT_EG_LC_CTRL_TAP_MEMORY_REGION)
125+
114126
enum OtEGSocDevice {
115127
OT_EG_SOC_DEV_ADC_CTRL,
116128
OT_EG_SOC_DEV_AES,
@@ -121,6 +133,7 @@ enum OtEGSocDevice {
121133
OT_EG_SOC_DEV_CSRNG,
122134
OT_EG_SOC_DEV_DM,
123135
OT_EG_SOC_DEV_DTM,
136+
OT_EG_SOC_DEV_LC_CTRL_DTM,
124137
OT_EG_SOC_DEV_EDN0,
125138
OT_EG_SOC_DEV_EDN1,
126139
OT_EG_SOC_DEV_ENTROPY_SRC,
@@ -148,13 +161,15 @@ enum OtEGSocDevice {
148161
OT_EG_SOC_DEV_ROM_CTRL,
149162
OT_EG_SOC_DEV_RSTMGR,
150163
OT_EG_SOC_DEV_RV_DM,
164+
OT_EG_SOC_DEV_DM_LC_CTRL,
151165
OT_EG_SOC_DEV_SENSOR_CTRL,
152166
OT_EG_SOC_DEV_SPI_DEVICE,
153167
OT_EG_SOC_DEV_SPI_HOST0,
154168
OT_EG_SOC_DEV_SPI_HOST1,
155169
OT_EG_SOC_DEV_SRAM_MAIN_CTRL,
156170
OT_EG_SOC_DEV_SYSRST_CTRL,
157171
OT_EG_SOC_DEV_TAP_CTRL,
172+
OT_EG_SOC_DEV_LC_CTRL_TAP_CTRL,
158173
OT_EG_SOC_DEV_TIMER,
159174
OT_EG_SOC_DEV_UART0,
160175
OT_EG_SOC_DEV_UART1,
@@ -196,6 +211,24 @@ enum OtEGBoardDevice {
196211
OT_EG_BOARD_DEV_COUNT,
197212
};
198213

214+
/*
215+
* <opentitan>/hw/ip/lc_ctrl/rtl/lc_ctrl.sv instantiates a DMI module (with
216+
* abits=7) and a DMI to TL-UL adapter. Together, they create a private bus,
217+
* exposing the LC Ctrl registers over JTAG <-> DTM <-> DMI <-> TL-UL. On the
218+
* DMI side we have the address space [0 .. 2^7); those addresses are mapped to
219+
* words on the TL-UL side, addressing [0 .. 2^7*4) bytes, and accessing the LC
220+
* Ctrl registers at the appropriate (documented) offset.
221+
*/
222+
#define OT_EG_LC_CTRL_TAP_DMI_ABIS 7u
223+
#define OT_EG_LC_CTRL_TAP_DMI_ADDR 0x0u
224+
#define OT_EG_LC_CTRL_TAP_DMI_SIZE (1u << OT_EG_LC_CTRL_TAP_DMI_ABIS)
225+
#define OT_EG_LC_CTRL_TAP_TL_ADDR 0x0u
226+
#define OT_EG_LC_CTRL_TAP_TL_SIZE ((1u << OT_EG_LC_CTRL_TAP_DMI_ABIS) * 4u)
227+
228+
#define OT_EG_LC_CTRL_TAP "ot-lc_ctrl-tap"
229+
#define OT_EG_LC_CTRL_TAP_XBAR OT_EG_LC_CTRL_TAP ".xbar"
230+
#define OT_EG_LC_CTRL_TAP_AS OT_EG_LC_CTRL_TAP ".as"
231+
199232
#define OT_EG_IBEX_WRAPPER_NUM_REGIONS 2u
200233

201234
static const uint8_t ot_eg_pmp_cfgs[] = {
@@ -361,6 +394,14 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
361394
IBEX_DEV_UINT_PROP("idcode", EG_RV_DM_TAP_IDCODE)
362395
),
363396
},
397+
[OT_EG_SOC_DEV_LC_CTRL_TAP_CTRL] = {
398+
.type = TYPE_TAP_CTRL_RBB,
399+
.cfg = &ot_eg_soc_lc_ctrl_tap_ctrl_configure,
400+
.prop = IBEXDEVICEPROPDEFS(
401+
IBEX_DEV_UINT_PROP("ir_length", IBEX_TAP_IR_LENGTH),
402+
IBEX_DEV_UINT_PROP("idcode", EG_LC_CTRL_TAP_IDCODE)
403+
),
404+
},
364405
[OT_EG_SOC_DEV_DTM] = {
365406
.type = TYPE_RISCV_DTM,
366407
.link = IBEXDEVICELINKDEFS(
@@ -370,6 +411,15 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
370411
IBEX_DEV_UINT_PROP("abits", 7u)
371412
),
372413
},
414+
[OT_EG_SOC_DEV_LC_CTRL_DTM] = {
415+
.type = TYPE_RISCV_DTM,
416+
.link = IBEXDEVICELINKDEFS(
417+
OT_EG_SOC_DEVLINK("tap-ctrl", LC_CTRL_TAP_CTRL)
418+
),
419+
.prop = IBEXDEVICEPROPDEFS(
420+
IBEX_DEV_UINT_PROP("abits", OT_EG_LC_CTRL_TAP_DMI_ABIS)
421+
),
422+
},
373423
[OT_EG_SOC_DEV_DM] = {
374424
.type = TYPE_RISCV_DM,
375425
.cfg = &ot_eg_soc_dm_configure,
@@ -742,7 +792,8 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
742792
[OT_EG_SOC_DEV_LC_CTRL] = {
743793
.type = TYPE_OT_LC_CTRL,
744794
.memmap = MEMMAPENTRIES(
745-
{ .base = 0x40140000u }
795+
{ .base = 0x40140000u },
796+
{ .base = LC_CTRL_TAP_MEMORY(OT_EG_LC_CTRL_TAP_TL_ADDR) }
746797
),
747798
.gpio = IBEXGPIOCONNDEFS(
748799
OT_EG_SOC_RSP(OT_PWRMGR_LC, PWRMGR),
@@ -1371,6 +1422,19 @@ static const IbexDeviceDef ot_eg_soc_devices[] = {
13711422
OT_EG_SOC_GPIO_ALERT(0, 40)
13721423
),
13731424
},
1425+
[OT_EG_SOC_DEV_DM_LC_CTRL] = {
1426+
.type = TYPE_OT_DM_TL,
1427+
.link = IBEXDEVICELINKDEFS(
1428+
OT_EG_SOC_DEVLINK("dtm", LC_CTRL_DTM),
1429+
OT_EG_SOC_DEVLINK("tl_dev", LC_CTRL)
1430+
),
1431+
.prop = IBEXDEVICEPROPDEFS(
1432+
IBEX_DEV_UINT_PROP("dmi_addr", OT_EG_LC_CTRL_TAP_DMI_ADDR),
1433+
IBEX_DEV_UINT_PROP("dmi_size", OT_EG_LC_CTRL_TAP_DMI_SIZE),
1434+
IBEX_DEV_UINT_PROP("tl_addr", OT_EG_LC_CTRL_TAP_TL_ADDR),
1435+
IBEX_DEV_STRING_PROP("tl_as_name", OT_EG_LC_CTRL_TAP_AS)
1436+
)
1437+
},
13741438
[OT_EG_SOC_DEV_PLIC] = {
13751439
.type = TYPE_SIFIVE_PLIC,
13761440
.memmap = MEMMAPENTRIES(
@@ -1616,6 +1680,20 @@ static void ot_eg_soc_tap_ctrl_configure(
16161680
}
16171681
}
16181682

1683+
static void ot_eg_soc_lc_ctrl_tap_ctrl_configure(
1684+
DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent)
1685+
{
1686+
(void)parent;
1687+
(void)def;
1688+
1689+
Chardev *chr;
1690+
1691+
chr = ibex_get_chardev_by_id("taprbb-lc-ctrl");
1692+
if (chr) {
1693+
qdev_prop_set_chr(dev, "chardev", chr);
1694+
}
1695+
}
1696+
16191697
static void ot_eg_soc_spi_device_configure(
16201698
DeviceState *dev, const IbexDeviceDef *def, DeviceState *parent)
16211699
{
@@ -1761,9 +1839,26 @@ static void ot_eg_soc_realize(DeviceState *dev, Error **errp)
17611839
ot_eg_soc_devices,
17621840
ARRAY_SIZE(ot_eg_soc_devices));
17631841

1764-
MemoryRegion *mrs[] = { get_system_memory(), NULL, NULL, NULL };
1765-
ibex_map_devices(s->devices, mrs, ot_eg_soc_devices,
1766-
ARRAY_SIZE(ot_eg_soc_devices));
1842+
MemoryRegion *lc_ctrl_tap_mr = g_new0(MemoryRegion, 1u);
1843+
memory_region_init(lc_ctrl_tap_mr, OBJECT(dev), OT_EG_LC_CTRL_TAP_XBAR,
1844+
OT_EG_LC_CTRL_TAP_TL_SIZE);
1845+
1846+
MemoryRegion *mrs[IBEX_MEMMAP_REGIDX_COUNT] = {
1847+
[OT_EG_DEFAULT_MEMORY_REGION] = get_system_memory(),
1848+
[OT_EG_LC_CTRL_TAP_MEMORY_REGION] = lc_ctrl_tap_mr,
1849+
};
1850+
ibex_map_devices_mask(s->devices, mrs, ot_eg_soc_devices,
1851+
ARRAY_SIZE(ot_eg_soc_devices),
1852+
IBEX_MEMMAP_MAKE_REG_MASK(
1853+
OT_EG_DEFAULT_MEMORY_REGION) |
1854+
IBEX_MEMMAP_MAKE_REG_MASK(
1855+
OT_EG_LC_CTRL_TAP_MEMORY_REGION));
1856+
Object *oas;
1857+
AddressSpace *as = g_new0(AddressSpace, 1u);
1858+
address_space_init(as, lc_ctrl_tap_mr, OT_EG_LC_CTRL_TAP_AS);
1859+
oas = object_new(TYPE_OT_ADDRESS_SPACE);
1860+
object_property_add_child(OBJECT(dev), as->name, oas);
1861+
ot_address_space_set(OT_ADDRESS_SPACE(oas), as);
17671862

17681863
qdev_connect_gpio_out_named(DEVICE(s->devices[OT_EG_SOC_DEV_RSTMGR]),
17691864
OT_RSTMGR_SOC_RST, 0,

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