[PYCDE] Assertion failed: "incorrect fold result type" during operation folding via Python API

[AnZhong24]

I encounter a crash when using PYCDE tool.
My original file is quite large, and unfortunately, it's been difficult to create a minimal reproducer. I've attached the full stack trace, and I hope it can provide some initial clues. Please let me know if there's any other information I can provide to help debug this.
Many thanks for your time and help!

The crash backtrace is as follows:

python: /project/llvm/mlir/lib/IR/Operation.cpp:626: void checkFoldResultTypes(mlir::Operation*, llvm::SmallVectorImpl<mlir::OpFoldResult>&): Assertion `false && "incorrect fold result type"' failed.
Stack dump without symbol names (ensure you have llvm-symbolizer in your PATH or set the environment var `LLVM_SYMBOLIZER_PATH` to point to it):
0  libPyCDE_CIRCTPythonCAPI.so 0x00007f659da0b588 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) + 40
1  libPyCDE_CIRCTPythonCAPI.so 0x00007f659da07ea5
2  libc.so.6                   0x00007f65a1c05520
3  libc.so.6                   0x00007f65a1c599fc pthread_kill + 300
4  libc.so.6                   0x00007f65a1c05476 raise + 22
5  libc.so.6                   0x00007f65a1beb7f3 abort + 211
6  libc.so.6                   0x00007f65a1beb71b
7  libc.so.6                   0x00007f65a1bfce96
8  libPyCDE_CIRCTPythonCAPI.so 0x00007f659db95c0c
9  libPyCDE_CIRCTPythonCAPI.so 0x00007f659db96ab8 mlir::Operation::fold(llvm::ArrayRef<mlir::Attribute>, llvm::SmallVectorImpl<mlir::OpFoldResult>&) + 72
10 libPyCDE_CIRCTPythonCAPI.so 0x00007f659db96db3 mlir::Operation::fold(llvm::SmallVectorImpl<mlir::OpFoldResult>&) + 547
11 libPyCDE_CIRCTPythonCAPI.so 0x00007f659dafbb54 mlir::OpBuilder::tryFold(mlir::Operation*, llvm::SmallVectorImpl<mlir::Value>&, llvm::SmallVectorImpl<mlir::Operation*>*) + 308
12 libPyCDE_CIRCTPythonCAPI.so 0x00007f659eafd160
13 libPyCDE_CIRCTPythonCAPI.so 0x00007f659eafd823 mlir::OperationConverter::convert(mlir::ConversionPatternRewriter&, mlir::Operation*) + 35
14 libPyCDE_CIRCTPythonCAPI.so 0x00007f659eaff25c mlir::OperationConverter::convertOperations(llvm::ArrayRef<mlir::Operation*>) + 316
15 libPyCDE_CIRCTPythonCAPI.so 0x00007f659eb01643 mlir::applyPartialConversion(mlir::Operation*, mlir::ConversionTarget const&, mlir::FrozenRewritePatternSet const&, mlir::ConversionConfig) + 131
16 libPyCDE_CIRCTPythonCAPI.so 0x00007f659e82dbb1
17 libPyCDE_CIRCTPythonCAPI.so 0x00007f659dc0d8e1 mlir::detail::OpToOpPassAdaptor::run(mlir::Pass*, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int) + 1249
18 libPyCDE_CIRCTPythonCAPI.so 0x00007f659dc0dd3a mlir::detail::OpToOpPassAdaptor::runPipeline(mlir::OpPassManager&, mlir::Operation*, mlir::AnalysisManager, bool, unsigned int, mlir::PassInstrumentor*, mlir::PassInstrumentation::PipelineParentInfo const*) + 362
19 libPyCDE_CIRCTPythonCAPI.so 0x00007f659dc0e0ae
20 libPyCDE_CIRCTPythonCAPI.so 0x00007f659dc0e27f
21 libPyCDE_CIRCTPythonCAPI.so 0x00007f659dbbebce
22 libPyCDE_CIRCTPythonCAPI.so 0x00007f659dbbf31b
23 libc.so.6                   0x00007f65a1c5cee8
24 libPyCDE_CIRCTPythonCAPI.so 0x00007f659dbbf29e
25 libPyCDE_CIRCTPythonCAPI.so 0x00007f659dbbf8af
26 libPyCDE_CIRCTPythonCAPI.so 0x00007f659d9ec16b llvm::StdThreadPool::processTasks(llvm::ThreadPoolTaskGroup*) + 555
27 libPyCDE_CIRCTPythonCAPI.so 0x00007f659d9ecf5a
28 libc.so.6                   0x00007f65a1c57ac3
29 libc.so.6                   0x00007f65a1ce98c0
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.

[teqdruid]

I can't do much with this stack trace unfortunately. You could get a slightly better one if you installed llvm-symbolizer as the comment says.

Also, what version of PyCDE are you using? At what point during execution is this stack trace occurring? I'm betting while it's running the CIRCT passes.

I don't know how familiar you are with CIRCT/MLIR, but if you call System.run_passes(debug=True), PyCDE will produce a bunch of asm files -- one per pass. This will enable us to determine what pass is at fault. If you can replicate the crash using circt-opt and the assembly file, you could use circt-reduce to reduce the asm to something more amenable to reporting. Unfortunately, neither circt-opt nor circt-reduce are included in the Python package.

[AnZhong24]

Thank you for your patient guidance and detailed instruction. I have tried to use the powerful tools.
Here is the reduced-mlir log print:

(env) ➜  disc_cpu_verilog git:(master) ✗ circt-opt reduced.mlir --lower-hw-to-sv 
reduced.mlir:36:10: error: 'comb.mux' op folder produced a value of incorrect type: 'i1', expected: 'ui1'
    %2 = comb.mux bin %curr_bank, %1, %0 {sv.namehint = "mux_curr_bank_in0_in1"} : ui1
         ^
reduced.mlir:36:10: note: see current operation: %6 = "comb.mux"(%arg10, %5, %4) <{twoState}> {sv.namehint = "mux_curr_bank_in0_in1"} : (i1, ui1, ui1) -> ui1
circt-opt: /home/zhonga/new/assassyn/3rd-party/circt/llvm/mlir/lib/IR/Operation.cpp:626: void checkFoldResultTypes(mlir::Operation*, llvm::SmallVectorImpl<mlir::OpFoldResult>&): Assertion `false && "incorrect fold result type"' failed.
PLEASE submit a bug report to https://github.com/llvm/circt and include the crash backtrace.
Stack dump:
0.	Program arguments: circt-opt reduced.mlir --lower-hw-to-sv

Here is the reduced mlir :

module {
  hw.module.extern @Top(in %clk : !seq.clock, in %rst : i1, out global_cycle_count : ui64, out global_finish : i1)
  hw.module.extern @sram_blackbox_array_b185f(in %clk : !seq.clock, in %rst_n : i1, in %address : i16, in %wd : i32, in %banksel : i1, in %read : i1, in %write : i1, out dataout : i32) attributes {output_file = #hw.output_file<"external_modules.sv", includeReplicatedOps>}
  hw.module.extern @sram_blackbox_array_4ebe9(in %clk : !seq.clock, in %rst_n : i1, in %address : i16, in %wd : i32, in %banksel : i1, in %read : i1, in %write : i1, out dataout : i32) attributes {output_file = #hw.output_file<"external_modules.sv", includeReplicatedOps>}
  hw.module.extern @array_d2b38(in %clk : !seq.clock, in %rst : i1, in %w_port0 : i1, in %widx_port0 : i4, in %wdata_port0 : i32, out q_out : !hw.array<16xi32>)
  hw.module.extern @array_52699(in %clk : !seq.clock, in %rst : i1, in %w_port0 : i1, in %widx_port0 : i4, in %wdata_port0 : i32, out q_out : !hw.array<16xi32>)
  hw.module.extern @array_526e9(in %clk : !seq.clock, in %rst : i1, in %w_port0 : i1, in %widx_port0 : i1, in %wdata_port0 : i16, out q_out : !hw.array<1xi16>)
  hw.module.extern @array_d403e(in %clk : !seq.clock, in %rst : i1, in %w_port0 : i1, in %widx_port0 : i1, in %wdata_port0 : i16, out q_out : !hw.array<1xi16>)
  hw.module.extern @array_d42ea(in %clk : !seq.clock, in %rst : i1, in %w_port0 : i1, in %widx_port0 : i1, in %wdata_port0 : i4, out q_out : !hw.array<2xi4>)
  hw.module.extern @array_db16d(in %clk : !seq.clock, in %rst : i1, in %w_port0 : i1, in %widx_port0 : i1, in %wdata_port0 : i32, out q_out : !hw.array<2xi32>)
  hw.module.extern @array_d88e2(in %clk : !seq.clock, in %rst : i1, out q_out : !hw.array<2xi4>)
  hw.module.extern @array_d898c(in %clk : !seq.clock, in %rst : i1, out q_out : !hw.array<2xi32>)
  hw.module.extern @array_d9fb5(in %clk : !seq.clock, in %rst : i1, in %w_port0 : i1, in %widx_port0 : i1, in %wdata_port0 : i1, out q_out : !hw.array<1xi1>)
  hw.module.extern @array_d9fc5(in %clk : !seq.clock, in %rst : i1, in %w_port0 : i1, in %widx_port0 : i1, in %wdata_port0 : i32, out q_out : !hw.array<1xi32>)
  hw.module.extern @array_d9ac6(in %clk : !seq.clock, in %rst : i1, in %w_port0 : i1, in %widx_port0 : i1, in %wdata_port0 : i32, out q_out : !hw.array<1xi32>)
  hw.module.extern @array_c4075(in %clk : !seq.clock, in %rst : i1, in %w_port0 : i1, in %widx_port0 : i1, in %wdata_port0 : i4, out q_out : !hw.array<1xi4>)
  hw.module.extern @array_c40ad(in %clk : !seq.clock, in %rst : i1, in %w_port0 : i1, in %widx_port0 : i1, in %wdata_port0 : si8, out q_out : !hw.array<1xsi8>)
  hw.module.extern @array_babee(in %clk : !seq.clock, in %rst : i1, in %w_port0 : i1, in %widx_port0 : i1, in %wdata_port0 : i1, out q_out : !hw.array<1xi1>)
  hw.module.extern @fifo<DEPTH_LOG2: i64, WIDTH: i64>(in %clk : !seq.clock, in %rst_n : i1, in %push_valid : i1, in %push_data : i32, in %pop_ready : i1, out push_ready : i1, out pop_valid : i1, out pop_data : i32) attributes {output_file = #hw.output_file<"external_modules.sv", includeReplicatedOps>}
  hw.module.extern @fifo_1<DEPTH_LOG2: i64, WIDTH: i64>(in %clk : !seq.clock, in %rst_n : i1, in %push_valid : i1, in %push_data : i32, in %pop_ready : i1, out push_ready : i1, out pop_valid : i1, out pop_data : i32) attributes {output_file = #hw.output_file<"external_modules.sv", includeReplicatedOps>}
  hw.module.extern @fifo_2<DEPTH_LOG2: i64, WIDTH: i64>(in %clk : !seq.clock, in %rst_n : i1, in %push_valid : i1, in %push_data : i4, in %pop_ready : i1, out push_ready : i1, out pop_valid : i1, out pop_data : i4) attributes {output_file = #hw.output_file<"external_modules.sv", includeReplicatedOps>}
  hw.module.extern @fifo_3<DEPTH_LOG2: i64, WIDTH: i64>(in %clk : !seq.clock, in %rst_n : i1, in %push_valid : i1, in %push_data : i1, in %pop_ready : i1, out push_ready : i1, out pop_valid : i1, out pop_data : i1) attributes {output_file = #hw.output_file<"external_modules.sv", includeReplicatedOps>}
  hw.module.extern @fifo_4<DEPTH_LOG2: i64, WIDTH: i64>(in %clk : !seq.clock, in %rst_n : i1, in %push_valid : i1, in %push_data : i108, in %pop_ready : i1, out push_ready : i1, out pop_valid : i1, out pop_data : i108) attributes {output_file = #hw.output_file<"external_modules.sv", includeReplicatedOps>}
  hw.module.extern @fifo_5<DEPTH_LOG2: i64, WIDTH: i64>(in %clk : !seq.clock, in %rst_n : i1, in %push_valid : i1, in %push_data : i1, in %pop_ready : i1, out push_ready : i1, out pop_valid : i1, out pop_data : i1) attributes {output_file = #hw.output_file<"external_modules.sv", includeReplicatedOps>}
  hw.module.extern @fifo_6<DEPTH_LOG2: i64, WIDTH: i64>(in %clk : !seq.clock, in %rst_n : i1, in %push_valid : i1, in %push_data : i4, in %pop_ready : i1, out push_ready : i1, out pop_valid : i1, out pop_data : i4) attributes {output_file = #hw.output_file<"external_modules.sv", includeReplicatedOps>}
  hw.module.extern @trigger_counter<WIDTH: i64>(in %clk : !seq.clock, in %rst_n : i1, in %delta : i8, in %pop_ready : i1, out delta_ready : i1, out pop_valid : i1) attributes {output_file = #hw.output_file<"external_modules.sv", includeReplicatedOps>}
  hw.module.extern @fetcher(in %clk : !seq.clock, in %rst : i1, in %cycle_count : ui64, in %trigger_counter_pop_valid : i1, in %array_d9ac6_q_in : !hw.array<1xi32>, out executed : i1, out finish : i1, out expose_fetcher_pc_addr : i32, out valid_fetcher_pc_addr : i1)
  hw.module.extern @decoder(in %clk : !seq.clock, in %rst : i1, in %cycle_count : ui64, in %trigger_counter_pop_valid : i1, in %rdata : i32, in %rdata_valid : i1, in %fetch_addr : i32, in %fetch_addr_valid : i1, in %inst_idx : i4, in %inst_idx_valid : i1, in %bank : i1, in %bank_valid : i1, in %fifo_execution_inst_idx_push_ready : i1, in %fifo_execution_signals_push_ready : i1, in %fifo_execution_curr_bank_push_ready : i1, in %fifo_execution_fetch_addr_push_ready : i1, in %execution_trigger_counter_delta_ready : i1, out executed : i1, out finish : i1, out rdata_pop_ready : i1, out fetch_addr_pop_ready : i1, out inst_idx_pop_ready : i1, out bank_pop_ready : i1, out execution_signals_push_valid : i1, out execution_signals_push_data : i108, out execution_inst_idx_push_valid : i1, out execution_inst_idx_push_data : i4, out execution_fetch_addr_push_valid : i1, out execution_fetch_addr_push_data : i32, out execution_curr_bank_push_valid : i1, out execution_curr_bank_push_data : i1, out execution_trigger : ui8, out expose_decoder_noop : i1, out valid_decoder_noop : i1, out expose_decoder_rdata : i32, out valid_decoder_rdata : i1, out expose_decoder_fetch_addr : i32, out valid_decoder_fetch_addr : i1, out expose_decoder__bd483 : i1, out valid_decoder__bd483 : i1, out expose_decoder_tmp_eq_4 : i1, out valid_decoder_tmp_eq_4 : i1, out expose_decoder__be869 : i4, out valid_decoder__be869 : i1, out expose_decoder_raw : i12, out valid_decoder_raw : i1, out expose_decoder_tmp_eq_9 : i1, out valid_decoder_tmp_eq_9 : i1, out expose_decoder__d8a69 : i4, out valid_decoder__d8a69 : i1, out expose_decoder_tmp_raw_1 : i12, out valid_decoder_tmp_raw_1 : i1, out expose_decoder_tmp_eq_14 : i1, out valid_decoder_tmp_eq_14 : i1, out expose_decoder__d9b4d : i4, out valid_decoder__d9b4d : i1, out expose_decoder_tmp_raw_2 : i12, out valid_decoder_tmp_raw_2 : i1, out expose_decoder_tmp_eq_19 : i1, out valid_decoder_tmp_eq_19 : i1, out expose_decoder__c02dd : i4, out valid_decoder__c02dd : i1, out expose_decoder_tmp_raw_3 : i12, out valid_decoder_tmp_raw_3 : i1, out expose_decoder_tmp_eq_24 : i1, out valid_decoder_tmp_eq_24 : i1, out expose_decoder__d4657 : i4, out valid_decoder__d4657 : i1, out expose_decoder_tmp_raw_4 : i12, out valid_decoder_tmp_raw_4 : i1, out expose_decoder_tmp_eq_29 : i1, out valid_decoder_tmp_eq_29 : i1, out expose_decoder__bdb35 : i4, out valid_decoder__bdb35 : i1, out expose_decoder_tmp_raw_5 : i12, out valid_decoder_tmp_raw_5 : i1, out expose_decoder_tmp_eq_34 : i1, out valid_decoder_tmp_eq_34 : i1, out expose_decoder__bdb9d : i4, out valid_decoder__bdb9d : i1, out expose_decoder_tmp_raw_6 : i12, out valid_decoder_tmp_raw_6 : i1, out expose_decoder_tmp_eq_39 : i1, out valid_decoder_tmp_eq_39 : i1, out expose_decoder__c2025 : i4, out valid_decoder__c2025 : i1, out expose_decoder_tmp_raw_7 : i12, out valid_decoder_tmp_raw_7 : i1, out expose_decoder__c206d : i1, out valid_decoder__c206d : i1, out expose_decoder__c20ad : i4, out valid_decoder__c20ad : i1, out expose_decoder_raw_2 : i5, out valid_decoder_raw_2 : i1, out expose_decoder__c2105 : i1, out valid_decoder__c2105 : i1, out expose_decoder__c214d : i4, out valid_decoder__c214d : i1, out expose_decoder_tmp_raw_2_1 : i5, out valid_decoder_tmp_raw_2_1 : i1, out expose_decoder__c219d : i1, out valid_decoder__c219d : i1, out expose_decoder__c21e5 : i4, out valid_decoder__c21e5 : i1, out expose_decoder_tmp_raw_2_2 : i5, out valid_decoder_tmp_raw_2_2 : i1, out expose_decoder__c2235 : i1, out valid_decoder__c2235 : i1, out expose_decoder__c227d : i4, out valid_decoder__c227d : i1, out expose_decoder__c2285 : i4, out valid_decoder__c2285 : i1, out expose_decoder__c22d5 : i1, out valid_decoder__c22d5 : i1, out expose_decoder__c2325 : i4, out valid_decoder__c2325 : i1, out expose_decoder__c232d : i4, out valid_decoder__c232d : i1, out expose_decoder__c237d : i1, out valid_decoder__c237d : i1, out expose_decoder__c23c5 : i4, out valid_decoder__c23c5 : i1, out expose_decoder__c23cd : i4, out valid_decoder__c23cd : i1, out expose_decoder__c4425 : i1, out valid_decoder__c4425 : i1, out expose_decoder__c446d : i4, out valid_decoder__c446d : i1, out expose_decoder__c4475 : i4, out valid_decoder__c4475 : i1, out expose_decoder__c44c5 : i1, out valid_decoder__c44c5 : i1, out expose_decoder__c450d : i4, out valid_decoder__c450d : i1, out expose_decoder__c4515 : i4, out valid_decoder__c4515 : i1, out expose_decoder__c4565 : i1, out valid_decoder__c4565 : i1, out expose_decoder__c459d : i4, out valid_decoder__c459d : i1, out expose_decoder__c20b5 : i4, out valid_decoder__c20b5 : i1, out expose_decoder__c45ed : i1, out valid_decoder__c45ed : i1, out expose_decoder__c4635 : i4, out valid_decoder__c4635 : i1, out expose_decoder__c463d : i4, out valid_decoder__c463d : i1, out expose_decoder__c468d : i1, out valid_decoder__c468d : i1, out expose_decoder__c46d5 : i4, out valid_decoder__c46d5 : i1, out expose_decoder__c46dd : i4, out valid_decoder__c46dd : i1, out expose_decoder__c472d : i1, out valid_decoder__c472d : i1, out expose_decoder__c4775 : i4, out valid_decoder__c4775 : i1, out expose_decoder__c477d : i4, out valid_decoder__c477d : i1, out expose_decoder__c47d5 : i1, out valid_decoder__c47d5 : i1, out expose_decoder__c6825 : i4, out valid_decoder__c6825 : i1, out expose_decoder__c682d : i4, out valid_decoder__c682d : i1, out expose_decoder__c687d : i1, out valid_decoder__c687d : i1, out expose_decoder__c68c5 : i4, out valid_decoder__c68c5 : i1, out expose_decoder__c68cd : i4, out valid_decoder__c68cd : i1, out expose_decoder_tmp_eq_2_4 : i1, out valid_decoder_tmp_eq_2_4 : i1, out expose_decoder__c696d : i4, out valid_decoder__c696d : i1, out expose_decoder__c6975 : i4, out valid_decoder__c6975 : i1, out expose_decoder_imm_2 : i14, out valid_decoder_imm_2 : i1, out expose_decoder_tmp_eq_3_4 : i1, out valid_decoder_tmp_eq_3_4 : i1, out expose_decoder__c6af5 : i4, out valid_decoder__c6af5 : i1, out expose_decoder__c6afd : i4, out valid_decoder__c6afd : i1, out expose_decoder_tmp_imm_3_3 : i14, out valid_decoder_tmp_imm_3_3 : i1, out expose_decoder_tmp_eq_3_9 : i1, out valid_decoder_tmp_eq_3_9 : i1, out expose_decoder__c6bf5 : i4, out valid_decoder__c6bf5 : i1, out expose_decoder__c9805 : i4, out valid_decoder__c9805 : i1, out expose_decoder_tmp_imm_3_7 : i14, out valid_decoder_tmp_imm_3_7 : i1, out expose_decoder_tmp_eq_3_14 : i1, out valid_decoder_tmp_eq_3_14 : i1, out expose_decoder__c98c5 : i4, out valid_decoder__c98c5 : i1, out expose_decoder__c98cd : i4, out valid_decoder__c98cd : i1, out expose_decoder_tmp_imm_3_11 : i14, out valid_decoder_tmp_imm_3_11 : i1, out expose_decoder_tmp_eq_3_19 : i1, out valid_decoder_tmp_eq_3_19 : i1, out expose_decoder__c998d : i4, out valid_decoder__c998d : i1, out expose_decoder__c9995 : i4, out valid_decoder__c9995 : i1, out expose_decoder_tmp_imm_3_15 : i14, out valid_decoder_tmp_imm_3_15 : i1, out expose_decoder_tmp_eq_3_24 : i1, out valid_decoder_tmp_eq_3_24 : i1, out expose_decoder__c9a55 : i4, out valid_decoder__c9a55 : i1, out expose_decoder__c9a5d : i4, out valid_decoder__c9a5d : i1, out expose_decoder_tmp_imm_3_19 : i14, out valid_decoder_tmp_imm_3_19 : i1, out expose_decoder_tmp_eq_3_29 : i1, out valid_decoder_tmp_eq_3_29 : i1, out expose_decoder__c9b0d : i4, out valid_decoder__c9b0d : i1, out expose_decoder__c9b15 : i4, out valid_decoder__c9b15 : i1, out expose_decoder_tmp_imm_3_23 : i14, out valid_decoder_tmp_imm_3_23 : i1, out expose_decoder_tmp_eq_4_1 : i1, out valid_decoder_tmp_eq_4_1 : i1, out expose_decoder_tmp_imm_4_3 : i22, out valid_decoder_tmp_imm_4_3 : i1, out expose_decoder__ab86d : i1, out valid_decoder__ab86d : i1, out expose_decoder__ab875 : i7, out valid_decoder__ab875 : i1, out expose_decoder__ab885 : i3, out valid_decoder__ab885 : i1, out expose_decoder__ab88d : i7, out valid_decoder__ab88d : i1, out expose_decoder__ab8ad : i1, out valid_decoder__ab8ad : i1, out expose_decoder_inst_idx : i4, out valid_decoder_inst_idx : i1)
  hw.module @execution(in %clk : !seq.clock, in %rst : i1, in %cycle_count : ui64, in %trigger_counter_pop_valid : i1, in %signals : i108, in %signals_valid : i1, in %fetch_addr : i32, in %fetch_addr_valid : i1, in %inst_idx : i4, in %inst_idx_valid : i1, in %curr_bank : i1, in %curr_bank_valid : i1, in %fifo_memory_access_result_push_ready : i1, in %fifo_memory_access_rd_push_ready : i1, in %fifo_memory_access_inst_idx_push_ready : i1, in %fifo_memory_access_bank_push_ready : i1, in %memory_access_trigger_counter_delta_ready : i1, in %array_d2b38_q_in : !hw.array<16xi32>, in %array_52699_q_in : !hw.array<16xi32>, in %array_526e9_q_in : !hw.array<1xi16>, in %array_d403e_q_in : !hw.array<1xi16>, in %array_d42ea_q_in : !hw.array<2xi4>, in %array_db16d_q_in : !hw.array<2xi32>, in %array_d88e2_q_in : !hw.array<2xi4>, in %array_d898c_q_in : !hw.array<2xi32>, in %array_d9fc5_q_in : !hw.array<1xi32>, out executed : i1, out finish : i1, out signals_pop_ready : i1, out fetch_addr_pop_ready : i1, out inst_idx_pop_ready : i1, out curr_bank_pop_ready : i1, out memory_access_bank_push_valid : i1, out memory_access_bank_push_data : i1, out memory_access_result_push_valid : i1, out memory_access_result_push_data : i32, out memory_access_inst_idx_push_valid : i1, out memory_access_inst_idx_push_data : i4, out memory_access_rd_push_valid : i1, out memory_access_rd_push_data : i4, out memory_access_trigger : ui8, out array_d42ea_w_port0 : i1, out array_d42ea_wdata_port0 : i4, out array_d42ea_widx_port0 : i1, out array_db16d_w_port0 : i1, out array_db16d_wdata_port0 : i32, out array_db16d_widx_port0 : i1, out array_d9fc5_w_port0 : i1, out array_d9fc5_wdata_port0 : i32, out array_d9fc5_widx_port0 : i1, out expose_execution_signals : i108, out valid_execution_signals : i1, out expose_execution_inst_idx_2 : i4, out valid_execution_inst_idx_2 : i1, out expose_execution_fetch_addr_2 : i32, out valid_execution_fetch_addr_2 : i1, out expose_execution_curr_bank : i1, out valid_execution_curr_bank : i1, out expose_execution_tmp_all_ready_2 : i1, out valid_execution_tmp_all_ready_2 : i1, out expose_execution__c08e9 : i1, out valid_execution__c08e9 : i1, out expose_execution_tmp_eq_41 : i1, out valid_execution_tmp_eq_41 : i1, out expose_execution_tmp_is_branch_2 : i1, out valid_execution_tmp_is_branch_2 : i1, out expose_execution_tmp_rs2_2 : i1, out valid_execution_tmp_rs2_2 : i1, out expose_execution__aeb8d : i1, out valid_execution__aeb8d : i1, out expose_execution_tmp_rs2_val_sel_3_1 : i32, out valid_execution_tmp_rs2_val_sel_3_1 : i1, out expose_execution__b1e6d : i1, out valid_execution__b1e6d : i1, out expose_execution__b1e95 : i4, out valid_execution__b1e95 : i1, out expose_execution_tmp_pred_val_sel_3_1 : i32, out valid_execution_tmp_pred_val_sel_3_1 : i1, out expose_execution_inst_idx : i4, out valid_execution_inst_idx : i1, out expose_execution_tmp_rs1_val_sel_3_1 : i32, out valid_execution_tmp_rs1_val_sel_3_1 : i1, out expose_execution_tmp_rs0_val_sel_3_1 : i32, out valid_execution_tmp_rs0_val_sel_3_1 : i1, out expose_execution_tmp_pred_active_1 : i1, out valid_execution_tmp_pred_active_1 : i1, out expose_execution__b1ff5 : i1, out valid_execution__b1ff5 : i1, out expose_execution_fetch_addr : i32, out valid_execution_fetch_addr : i1, out expose_execution_tmp_imm_2_2 : i1, out valid_execution_tmp_imm_2_2 : i1, out expose_execution_tmp_eq_2_5 : i32, out valid_execution_tmp_eq_2_5 : i1, out expose_execution_tmp_memory_read_1 : i1, out valid_execution_tmp_memory_read_1 : i1, out expose_execution_tmp_memory_write_1 : i1, out valid_execution_tmp_memory_write_1 : i1, out expose_execution_tmp_adder_result_cast_2 : i32, out valid_execution_tmp_adder_result_cast_2 : i1, out expose_execution_request_addr : i16, out valid_execution_request_addr : i1) attributes {output_file = #hw.output_file<"execution.sv", includeReplicatedOps>} {
    %false = hw.constant false
    %c0_i32 = hw.constant 0 : i32
    %c0_i4 = hw.constant 0 : i4
    %c0_i16 = hw.constant 0 : i16
    %0 = hwarith.constant 0 : ui1
    %1 = hwarith.constant 1 : ui1
    %2 = comb.mux bin %curr_bank, %1, %0 {sv.namehint = "mux_curr_bank_in0_in1"} : ui1
    %3 = comb.mux bin %curr_bank, %1, %2 {sv.namehint = "mux_curr_bank_mux_curr_bank_in0_in1_in1"} : ui1
    %4 = comb.mux bin %false, %0, %3 {sv.namehint = "mux_inv_curr_bank_mux_curr_bank_mux_curr_bank_in0_in1_in1_in1"} : ui1
    %5 = comb.mux bin %false, %0, %4 {sv.namehint = "mux_inv_curr_bank_mux_inv_curr_bank_mux_curr_bank_mux_curr_bank_in0_in1_in1_in1_in1"} : ui1
    %6 = hwarith.cast %5 {sv.namehint = "mux_inv_curr_bank_mux_inv_curr_bank_mux_curr_bank_mux_curr_bank_in0_in1_in1_in1_in1"} : (ui1) -> i1
    %c0_i8 = hw.constant 0 : i8
    %7 = hwarith.cast %c0_i8 {sv.namehint = "mux_None_in0_in1_0upto8"} : (i8) -> ui8
    hw.output %false, %false, %false, %false, %false, %false, %false, %curr_bank, %false, %c0_i32, %false, %inst_idx, %false, %c0_i4, %7, %false, %c0_i4, %6, %false, %c0_i32, %false, %false, %c0_i32, %false, %signals, %false, %inst_idx, %false, %fetch_addr, %false, %curr_bank, %false, %false, %false, %false, %false, %false, %false, %false, %false, %false, %false, %false, %false, %c0_i32, %false, %false, %false, %c0_i4, %false, %c0_i32, %false, %inst_idx, %false, %c0_i32, %false, %c0_i32, %false, %false, %false, %false, %false, %fetch_addr, %false, %false, %false, %c0_i32, %false, %false, %false, %false, %false, %c0_i32, %false, %c0_i16, %false : i1, i1, i1, i1, i1, i1, i1, i1, i1, i32, i1, i4, i1, i4, ui8, i1, i4, i1, i1, i32, i1, i1, i32, i1, i108, i1, i4, i1, i32, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i1, i32, i1, i1, i1, i4, i1, i32, i1, i4, i1, i32, i1, i32, i1, i1, i1, i1, i1, i32, i1, i1, i1, i32, i1, i1, i1, i1, i1, i32, i1, i16, i1
  }
  hw.module.extern @writeback(in %clk : !seq.clock, in %rst : i1, in %cycle_count : ui64, in %trigger_counter_pop_valid : i1, in %rd : i4, in %rd_valid : i1, in %mdata : i32, in %mdata_valid : i1, in %bank : i1, in %bank_valid : i1, in %inst_idx : i4, in %inst_idx_valid : i1, in %array_d2b38_q_in : !hw.array<16xi32>, in %array_52699_q_in : !hw.array<16xi32>, out executed : i1, out finish : i1, out rd_pop_ready : i1, out mdata_pop_ready : i1, out bank_pop_ready : i1, out inst_idx_pop_ready : i1, out array_d2b38_w_port0 : i1, out array_d2b38_wdata_port0 : i32, out array_d2b38_widx_port0 : i4, out array_52699_w_port0 : i1, out array_52699_wdata_port0 : i32, out array_52699_widx_port0 : i4, out expose_writeback_bank : i1, out valid_writeback_bank : i1, out expose_writeback_inst_idx : i4, out valid_writeback_inst_idx : i1, out expose_writeback__b631d : i1, out valid_writeback__b631d : i1, out expose_writeback_rd : i4, out valid_writeback_rd : i1, out expose_writeback_mdata : i32, out valid_writeback_mdata : i1)
  hw.module.extern @memory_access(in %clk : !seq.clock, in %rst : i1, in %cycle_count : ui64, in %trigger_counter_pop_valid : i1, in %rdata : i32, in %rdata_valid : i1, in %rd : i4, in %rd_valid : i1, in %bank : i1, in %bank_valid : i1, in %result : i32, in %result_valid : i1, in %inst_idx : i4, in %inst_idx_valid : i1, in %fifo_writeback_bank_push_ready : i1, in %fifo_writeback_rd_push_ready : i1, in %fifo_writeback_mdata_push_ready : i1, in %fifo_writeback_inst_idx_push_ready : i1, in %writeback_trigger_counter_delta_ready : i1, out executed : i1, out finish : i1, out rdata_pop_ready : i1, out rd_pop_ready : i1, out bank_pop_ready : i1, out result_pop_ready : i1, out inst_idx_pop_ready : i1, out writeback_mdata_push_valid : i1, out writeback_mdata_push_data : i32, out writeback_rd_push_valid : i1, out writeback_rd_push_data : i4, out writeback_bank_push_valid : i1, out writeback_bank_push_data : i1, out writeback_inst_idx_push_valid : i1, out writeback_inst_idx_push_data : i4, out writeback_trigger : ui8, out expose_memory_access_tmp_wb_data_sel_1 : i32, out valid_memory_access_tmp_wb_data_sel_1 : i1)
  hw.module.extern @Driver(in %clk : !seq.clock, in %rst : i1, in %cycle_count : ui64, in %trigger_counter_pop_valid : i1, in %fetcher_trigger_counter_delta_ready : i1, out executed : i1, out finish : i1, out fetcher_trigger : ui8)
  hw.module.extern @dcache(in %clk : !seq.clock, in %rst : i1, in %cycle_count : ui64, in %execution_executed : i1, in %execution_tmp_memory_write_1 : i1, in %execution_tmp_memory_write_1_valid : i1, in %execution_request_addr : i16, in %execution_request_addr_valid : i1, in %execution_tmp_rs2_val_sel_3_1 : i32, in %execution_tmp_rs2_val_sel_3_1_valid : i1, in %execution_tmp_memory_read_1 : i1, in %execution_tmp_memory_read_1_valid : i1, in %mem_dataout : i32, in %fifo_memory_access_rdata_push_ready : i1, out executed : i1, out finish : i1, out mem_address : i16, out mem_write_data : i32, out mem_write_enable : i1, out mem_read_enable : i1, out memory_access_rdata_push_valid : i1, out memory_access_rdata_push_data : i32)
  hw.module.extern @fetcher_impl(in %clk : !seq.clock, in %rst : i1, in %cycle_count : ui64, in %writeback_executed : i1, in %decoder_executed : i1, in %fetcher_executed : i1, in %execution_executed : i1, in %decoder_noop : i1, in %decoder_noop_valid : i1, in %execution_tmp_all_ready_2 : i1, in %execution_tmp_all_ready_2_valid : i1, in %writeback_inst_idx_3 : i4, in %writeback_inst_idx_3_valid : i1, in %writeback_bank_3 : i1, in %writeback_bank_3_valid : i1, in %fetcher_pc_addr : i32, in %fetcher_pc_addr_valid : i1, in %fifo_decoder_fetch_addr_push_ready : i1, in %fifo_decoder_bank_push_ready : i1, in %fifo_decoder_inst_idx_push_ready : i1, in %decoder_trigger_counter_delta_ready : i1, in %array_526e9_q_in : !hw.array<1xi16>, in %array_d403e_q_in : !hw.array<1xi16>, in %array_d9fb5_q_in : !hw.array<1xi1>, in %array_d9fc5_q_in : !hw.array<1xi32>, in %array_d9ac6_q_in : !hw.array<1xi32>, in %array_c4075_q_in : !hw.array<1xi4>, in %array_c40ad_q_in : !hw.array<1xsi8>, in %array_babee_q_in : !hw.array<1xi1>, out executed : i1, out finish : i1, out decoder_fetch_addr_push_valid : i1, out decoder_fetch_addr_push_data : i32, out decoder_inst_idx_push_valid : i1, out decoder_inst_idx_push_data : i4, out decoder_bank_push_valid : i1, out decoder_bank_push_data : i1, out decoder_trigger : ui8, out array_526e9_w_port0 : i1, out array_526e9_wdata_port0 : i16, out array_526e9_widx_port0 : i1, out array_d403e_w_port0 : i1, out array_d403e_wdata_port0 : i16, out array_d403e_widx_port0 : i1, out array_d9fb5_w_port0 : i1, out array_d9fb5_wdata_port0 : i1, out array_d9fb5_widx_port0 : i1, out array_d9ac6_w_port0 : i1, out array_d9ac6_wdata_port0 : i32, out array_d9ac6_widx_port0 : i1, out array_c4075_w_port0 : i1, out array_c4075_wdata_port0 : i4, out array_c4075_widx_port0 : i1, out array_c40ad_w_port0 : i1, out array_c40ad_wdata_port0 : si8, out array_c40ad_widx_port0 : i1, out array_babee_w_port0 : i1, out array_babee_wdata_port0 : i1, out array_babee_widx_port0 : i1, out expose_fetcher_impl_real_fetch : i1, out valid_fetcher_impl_real_fetch : i1, out expose_fetcher_impl__ba285 : i16, out valid_fetcher_impl__ba285 : i1, out expose_fetcher_impl_target_pc_sel : i32, out valid_fetcher_impl_target_pc_sel : i1, out expose_fetcher_impl_inst_idx_sel : i4, out valid_fetcher_impl_inst_idx_sel : i1)
  hw.module.extern @icache(in %clk : !seq.clock, in %rst : i1, in %cycle_count : ui64, in %fetcher_impl_executed : i1, in %fetcher_impl_port_ba285 : i16, in %fetcher_impl_port_ba285_valid : i1, in %fetcher_impl_real_fetch : i1, in %fetcher_impl_real_fetch_valid : i1, in %mem_dataout : i32, in %fifo_decoder_rdata_push_ready : i1, out executed : i1, out finish : i1, out mem_address : i16, out mem_write_data : i32, out mem_write_enable : i1, out mem_read_enable : i1, out decoder_rdata_push_valid : i1, out decoder_rdata_push_data : i32)
}

Many thanks again for your time and patience.

[uenoku]

I think this part is causing an assertion failure in your code.

circt/lib/Dialect/Comb/CombFolds.cpp

Lines 1919 to 1923 in e589add

	if (auto tv = dyn_cast_or_null<IntegerAttr>(adaptor.getTrueValue()))
	if (auto fv = dyn_cast_or_null<IntegerAttr>(adaptor.getFalseValue()))
	if (tv.getValue().isOne() && fv.getValue().isZero() &&
	hw::getBitWidth(getType()) == 1 && getCond() != getResult())
	return getCond();

This part returns %curr_bank as a fold result but it has a type i1, whereas operand has ui1. I think the easiest fix is to insert a check that types are equivalent.