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libxscale: Add xscale needed kernel headers
This patch adds xscale needed kernel abi headers into the kernel-headers directory. Signed-off-by: Tian Xin <[email protected]> Signed-off-by: Wei Honggang <[email protected]> Signed-off-by: Zhao Qianwei <[email protected]> Signed-off-by: Li Qiang <[email protected]> Signed-off-by: Yan Lei <[email protected]>
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‎kernel-headers/CMakeLists.txt‎

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@@ -26,6 +26,8 @@ publish_internal_headers(rdma
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rdma/rvt-abi.h
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rdma/siw-abi.h
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rdma/vmw_pvrdma-abi.h
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rdma/xsc-abi.h
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rdma/xsc_user_ioctl_cmds.h
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)
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publish_internal_headers(rdma/hfi
@@ -80,6 +82,7 @@ rdma_kernel_provider_abi(
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rdma/rdma_user_rxe.h
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rdma/siw-abi.h
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rdma/vmw_pvrdma-abi.h
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rdma/xsc-abi.h
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)
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publish_headers(infiniband

‎kernel-headers/rdma/ib_user_ioctl_verbs.h‎

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@@ -255,6 +255,7 @@ enum rdma_driver_id {
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RDMA_DRIVER_SIW,
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RDMA_DRIVER_ERDMA,
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RDMA_DRIVER_MANA,
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RDMA_DRIVER_XSC = 1,
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};
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enum ib_uverbs_gid_type {

‎kernel-headers/rdma/xsc-abi.h‎

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 - 2022, Shanghai Yunsilicon Technology Co., Ltd.
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* All rights reserved.
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*/
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#ifndef XSC_ABI_USER_H
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#define XSC_ABI_USER_H
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#include <linux/types.h>
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#include <linux/if_ether.h> /* For ETH_ALEN. */
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#include <rdma/ib_user_ioctl_verbs.h>
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enum {
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XSC_WQ_FLAG_SIGNATURE = 1 << 0,
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};
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/* Make sure that all structs defined in this file remain laid out so
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* that they pack the same way on 32-bit and 64-bit architectures (to
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* avoid incompatibility between 32-bit userspace and 64-bit kernels).
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* In particular do not use pointer types -- pass pointers in __u64
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* instead.
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*/
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struct xsc_ib_alloc_ucontext_req {
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__u32 rsvd0;
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__u32 rsvd1;
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};
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enum xsc_user_cmds_supp_uhw {
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XSC_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
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XSC_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
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};
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struct xsc_ib_alloc_ucontext_resp {
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__u32 qp_tab_size;
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__u32 cache_line_size;
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__u16 max_sq_desc_sz;
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__u16 max_rq_desc_sz;
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__u32 max_send_wqebb;
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__u32 max_recv_wr;
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__u16 num_ports;
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__u16 device_id;
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__aligned_u64 qpm_tx_db;
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__aligned_u64 qpm_rx_db;
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__aligned_u64 cqm_next_cid_reg;
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__aligned_u64 cqm_armdb;
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__u32 send_ds_num;
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__u32 recv_ds_num;
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__u32 cmds_supp_uhw;
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};
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struct xsc_ib_create_qp {
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__aligned_u64 buf_addr;
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__aligned_u64 db_addr;
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__u32 sq_wqe_count;
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__u32 rq_wqe_count;
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__u32 rq_wqe_shift;
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__u32 flags;
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};
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struct xsc_ib_create_qp_resp {
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__u32 bfreg_index;
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__u32 resv;
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};
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struct xsc_ib_create_cq {
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__aligned_u64 buf_addr;
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__aligned_u64 db_addr;
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__u32 cqe_size;
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};
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struct xsc_ib_create_cq_resp {
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__u32 cqn;
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__u32 reserved;
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};
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struct xsc_ib_create_ah_resp {
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__u32 response_length;
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__u8 dmac[ETH_ALEN];
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__u8 reserved[6];
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};
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struct xsc_ib_alloc_pd_resp {
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__u32 pdn;
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};
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struct xsc_ib_tso_caps {
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__u32 max_tso; /* Maximum tso payload size in bytes */
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/* Corresponding bit will be set if qp type from
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* 'enum ib_qp_type' is supported, e.g.
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* supported_qpts |= 1 << IB_QPT_UD
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*/
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__u32 supported_qpts;
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};
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/* RX Hash function flags */
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enum xsc_rx_hash_function_flags {
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XSC_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
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};
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/*
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* RX Hash flags, these flags allows to set which incoming packet's field should
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* participates in RX Hash. Each flag represent certain packet's field,
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* when the flag is set the field that is represented by the flag will
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* participate in RX Hash calculation.
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* Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
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* and *TCP and *UDP flags can't be enabled together on the same QP.
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*/
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enum xsc_rx_hash_fields {
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XSC_RX_HASH_SRC_IPV4 = 1 << 0,
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XSC_RX_HASH_DST_IPV4 = 1 << 1,
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XSC_RX_HASH_SRC_IPV6 = 1 << 2,
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XSC_RX_HASH_DST_IPV6 = 1 << 3,
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XSC_RX_HASH_SRC_PORT_TCP = 1 << 4,
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XSC_RX_HASH_DST_PORT_TCP = 1 << 5,
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XSC_RX_HASH_SRC_PORT_UDP = 1 << 6,
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XSC_RX_HASH_DST_PORT_UDP = 1 << 7,
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XSC_RX_HASH_IPSEC_SPI = 1 << 8,
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/* Save bits for future fields */
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XSC_RX_HASH_INNER = (1UL << 31),
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};
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struct xsc_ib_rss_caps {
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__aligned_u64 rx_hash_fields_mask; /* enum xsc_rx_hash_fields */
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__u8 rx_hash_function; /* enum xsc_rx_hash_function_flags */
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__u8 reserved[7];
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};
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enum xsc_ib_cqe_comp_res_format {
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XSC_IB_CQE_RES_FORMAT_HASH = 1 << 0,
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XSC_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
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XSC_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2,
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};
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struct xsc_ib_cqe_comp_caps {
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__u32 max_num;
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__u32 supported_format; /* enum xsc_ib_cqe_comp_res_format */
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};
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enum xsc_ib_packet_pacing_cap_flags {
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XSC_IB_PP_SUPPORT_BURST = 1 << 0,
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};
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struct xsc_packet_pacing_caps {
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__u32 qp_rate_limit_min;
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__u32 qp_rate_limit_max; /* In kpbs */
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/* Corresponding bit will be set if qp type from
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* 'enum ib_qp_type' is supported, e.g.
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* supported_qpts |= 1 << IB_QPT_RAW_PACKET
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*/
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__u32 supported_qpts;
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__u8 cap_flags; /* enum xsc_ib_packet_pacing_cap_flags */
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__u8 reserved[3];
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};
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enum xsc_ib_mpw_caps {
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MPW_RESERVED = 1 << 0,
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XSC_IB_ALLOW_MPW = 1 << 1,
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XSC_IB_SUPPORT_EMPW = 1 << 2,
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};
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enum xsc_ib_sw_parsing_offloads {
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XSC_IB_SW_PARSING = 1 << 0,
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XSC_IB_SW_PARSING_CSUM = 1 << 1,
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XSC_IB_SW_PARSING_LSO = 1 << 2,
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};
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struct xsc_ib_sw_parsing_caps {
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__u32 sw_parsing_offloads; /* enum xsc_ib_sw_parsing_offloads */
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/* Corresponding bit will be set if qp type from
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* 'enum ib_qp_type' is supported, e.g.
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* supported_qpts |= 1 << IB_QPT_RAW_PACKET
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*/
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__u32 supported_qpts;
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};
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struct xsc_ib_striding_rq_caps {
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__u32 min_single_stride_log_num_of_bytes;
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__u32 max_single_stride_log_num_of_bytes;
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__u32 min_single_wqe_log_num_of_strides;
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__u32 max_single_wqe_log_num_of_strides;
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/* Corresponding bit will be set if qp type from
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* 'enum ib_qp_type' is supported, e.g.
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* supported_qpts |= 1 << IB_QPT_RAW_PACKET
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*/
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__u32 supported_qpts;
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__u32 reserved;
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};
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enum xsc_ib_query_dev_resp_flags {
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/* Support 128B CQE compression */
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XSC_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
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XSC_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
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};
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enum xsc_ib_tunnel_offloads {
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XSC_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0,
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XSC_IB_TUNNELED_OFFLOADS_GRE = 1 << 1,
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XSC_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2,
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XSC_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3,
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XSC_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4,
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};
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struct xsc_ib_query_device_resp {
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__u32 comp_mask;
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__u32 response_length;
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struct xsc_ib_tso_caps tso_caps;
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struct xsc_ib_rss_caps rss_caps;
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struct xsc_ib_cqe_comp_caps cqe_comp_caps;
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struct xsc_packet_pacing_caps packet_pacing_caps;
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__u32 xsc_ib_support_multi_pkt_send_wqes;
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__u32 flags; /* Use enum xsc_ib_query_dev_resp_flags */
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struct xsc_ib_sw_parsing_caps sw_parsing_caps;
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struct xsc_ib_striding_rq_caps striding_rq_caps;
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__u32 tunnel_offloads_caps; /* enum xsc_ib_tunnel_offloads */
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__u32 reserved;
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};
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struct xsc_ib_burst_info {
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__u32 max_burst_sz;
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__u16 typical_pkt_sz;
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__u16 reserved;
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};
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struct xsc_ib_modify_qp {
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__u32 comp_mask;
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struct xsc_ib_burst_info burst_info;
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__u32 reserved;
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};
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struct xsc_ib_modify_qp_resp {
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__u32 response_length;
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__u32 dctn;
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};
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#endif /* XSC_ABI_USER_H */

‎kernel-headers/rdma/xsc_user_ioctl_cmds.h‎

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 - 2022, Shanghai Yunsilicon Technology Co., Ltd.
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* All rights reserved.
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*/
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#ifndef XSC_USER_IOCTL_CMDS_H
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#define XSC_USER_IOCTL_CMDS_H
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#include <linux/types.h>
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#include <rdma/ib_user_ioctl_cmds.h>
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enum xsc_ib_devx_methods {
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XSC_IB_METHOD_DEVX_OTHER = (1U << UVERBS_ID_NS_SHIFT),
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XSC_IB_METHOD_DEVX_QUERY_UAR,
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XSC_IB_METHOD_DEVX_QUERY_EQN,
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};
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enum xsc_ib_devx_other_attrs {
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XSC_IB_ATTR_DEVX_OTHER_CMD_IN = (1U << UVERBS_ID_NS_SHIFT),
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XSC_IB_ATTR_DEVX_OTHER_CMD_OUT,
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};
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enum xsc_ib_objects {
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XSC_IB_OBJECT_DEVX = (1U << UVERBS_ID_NS_SHIFT),
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XSC_IB_OBJECT_DEVX_OBJ,
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XSC_IB_OBJECT_DEVX_UMEM,
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XSC_IB_OBJECT_FLOW_MATCHER,
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};
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#endif

‎libibverbs/verbs.h‎

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@@ -2277,6 +2277,7 @@ extern const struct verbs_device_ops verbs_provider_qedr;
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extern const struct verbs_device_ops verbs_provider_rxe;
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extern const struct verbs_device_ops verbs_provider_siw;
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extern const struct verbs_device_ops verbs_provider_vmw_pvrdma;
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extern const struct verbs_device_ops verbs_provider_xscale;
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extern const struct verbs_device_ops verbs_provider_all;
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extern const struct verbs_device_ops verbs_provider_none;
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void ibv_static_providers(void *unused, ...);

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