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Vectorizer Enable Select and CMP by default
IGCVectorizer now vectorizes uniform CMP and Select instructions by defaut, igc legalizer pass is configured to pass through vectorized selects of the types that are i32 and float.
1 parent 6b0e4b6 commit ddc7a1d

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7 files changed

+81
-33
lines changed

7 files changed

+81
-33
lines changed

‎IGC/Compiler/CISACodeGen/IGCVectorizer.cpp‎

Lines changed: 20 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -762,17 +762,28 @@ bool IGCVectorizer::collectOperandsForVectorization(unsigned OperNumToStart, uns
762762

763763
bool IGCVectorizer::handleCMPInstruction(VecArr& Slice){
764764

765-
bool IsSliceUniform = true;
766-
for (auto El : Slice)
767-
IsSliceUniform &= WI->isUniform(El);
765+
bool IsSliceUniform = true;
766+
for (auto El : Slice) {
767+
IsSliceUniform &= WI->isUniform(El);
768+
// we must process users as well
769+
// because we do not support
770+
// bit flag extraction from predicates
771+
for (auto User : El->users()) {
772+
bool UserIsUniform = WI->isUniform(User);
773+
if (!UserIsUniform) {
774+
PRINT_LOG("User is not uniform: "); PRINT_INST_NL(User);
775+
}
776+
IsSliceUniform &= UserIsUniform;
777+
}
778+
}
768779

769-
if (!IsSliceUniform) {
770-
PRINT_LOG_NL("Select is stub vectorized, not uniform");
771-
return true;
772-
}
780+
if (!IsSliceUniform) {
781+
PRINT_LOG_NL("Select is stub vectorized, not uniform");
782+
return true;
783+
}
773784

774-
if (!IGC_GET_FLAG_VALUE(VectorizerAllowUniformCMP))
775-
return true;
785+
if (!IGC_GET_FLAG_VALUE(VectorizerAllowUniformCMP))
786+
return true;
776787

777788
Instruction *First = Slice.front();
778789
Value *PrevVectorization = nullptr;

‎IGC/Compiler/tests/IGCVectorizer/vectorizer-insert-pattern-inbetween.ll‎

Lines changed: 25 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,11 @@
1+
;=========================== begin_copyright_notice ============================
2+
;
3+
; Copyright (C) 2025 Intel Corporation
4+
;
5+
; SPDX-License-Identifier: MIT
6+
;
7+
;============================ end_copyright_notice =============================
8+
19
; REQUIRES: regkeys
210
; RUN: igc_opt -S --igc-vectorizer -dce --regkey=VectorizerAllowSelect=1 --regkey=VectorizerAllowCMP=1 --regkey=VectorizerAllowMAXNUM=1 --regkey=VectorizerAllowWAVEALL=1 --regkey=VectorizerDepWindowMultiplier=4 < %s 2>&1 | FileCheck %s
311

@@ -13,29 +21,29 @@
1321
; CHECK: [[insrt_5:%.*]] = insertelement <8 x float> [[insrt_4]]
1422
; CHECK: [[insrt_6:%.*]] = insertelement <8 x float> [[insrt_5]], float [[fmul2]], i32 6
1523
; CHECK: [[insrt_7:%.*]] = insertelement <8 x float> [[insrt_6]]
16-
; CHECK: %vectorized_binary = fmul <8 x float> %vector38, <float 1.250000e-01, float 0x3FF7154760000000, float 0x3FF7154760000000, float 0x3FF7154760000000, float 0x3FF7154760000000, float 0x3FF7154760000000, float 0x3FF7154760000000, float 0x3FF7154760000000>
17-
; CHECK: %vector_extract39 = extractelement <8 x float> %vectorized_binary, i32 0
18-
; CHECK: %vector_extract40 = extractelement <8 x float> %vectorized_binary, i32 1
19-
; CHECK: %vector_extract41 = extractelement <8 x float> %vectorized_binary, i32 2
20-
; CHECK: %vector_extract42 = extractelement <8 x float> %vectorized_binary, i32 3
21-
; CHECK: %vector_extract43 = extractelement <8 x float> %vectorized_binary, i32 4
22-
; CHECK: %vector_extract44 = extractelement <8 x float> %vectorized_binary, i32 5
23-
; CHECK: %vector_extract45 = extractelement <8 x float> %vectorized_binary, i32 6
24-
; CHECK: %vector_extract46 = extractelement <8 x float> %vectorized_binary, i32 7
24+
; CHECK: %vectorized_binary = fmul <8 x float> [[insrt_7]], <float 1.250000e-01, float 0x3FF7154760000000, float 0x3FF7154760000000, float 0x3FF7154760000000, float 0x3FF7154760000000, float 0x3FF7154760000000, float 0x3FF7154760000000, float 0x3FF7154760000000>
25+
; CHECK: [[extrct_0:%.*]] = extractelement <8 x float> %vectorized_binary, i32 0
26+
; CHECK: [[extrct_1:%.*]] = extractelement <8 x float> %vectorized_binary, i32 1
27+
; CHECK: [[extrct_2:%.*]] = extractelement <8 x float> %vectorized_binary, i32 2
28+
; CHECK: [[extrct_3:%.*]] = extractelement <8 x float> %vectorized_binary, i32 3
29+
; CHECK: [[extrct_4:%.*]] = extractelement <8 x float> %vectorized_binary, i32 4
30+
; CHECK: [[extrct_5:%.*]] = extractelement <8 x float> %vectorized_binary, i32 5
31+
; CHECK: [[extrct_6:%.*]] = extractelement <8 x float> %vectorized_binary, i32 6
32+
; CHECK: [[extrct_7:%.*]] = extractelement <8 x float> %vectorized_binary, i32 7
2533
; CHECK: %19 = icmp slt i32 %2, 1
2634
; CHECK: %20 = icmp slt i32 1, %.pn1482
2735
; CHECK: %21 = icmp slt i32 %3, %.pn1482
2836
; CHECK: %22 = icmp slt i32 %4, 1
2937
; CHECK: %23 = icmp slt i32 %5, 1
3038
; CHECK: %24 = icmp slt i32 %6, %.pn1482
31-
; CHECK: %25 = select i1 %19, float 0xFFF0000000000000, float %vector_extract39
32-
; CHECK: %26 = select i1 %20, float 0xFFF0000000000000, float %vector_extract40
33-
; CHECK: %27 = select i1 %21, float 0xFFF0000000000000, float %vector_extract41
34-
; CHECK: %28 = select i1 %20, float 0xFFF0000000000000, float %vector_extract42
35-
; CHECK: %29 = select i1 %22, float 0xFFF0000000000000, float %vector_extract43
36-
; CHECK: %30 = select i1 %23, float 0xFFF0000000000000, float %vector_extract44
37-
; CHECK: %31 = select i1 %24, float 0xFFF0000000000000, float %vector_extract45
38-
; CHECK: %32 = select i1 %20, float 0xFFF0000000000000, float %vector_extract46
39+
; CHECK: %25 = select i1 %19, float 0xFFF0000000000000, float [[extrct_0]]
40+
; CHECK: %26 = select i1 %20, float 0xFFF0000000000000, float [[extrct_1]]
41+
; CHECK: %27 = select i1 %21, float 0xFFF0000000000000, float [[extrct_2]]
42+
; CHECK: %28 = select i1 %20, float 0xFFF0000000000000, float [[extrct_3]]
43+
; CHECK: %29 = select i1 %22, float 0xFFF0000000000000, float [[extrct_4]]
44+
; CHECK: %30 = select i1 %23, float 0xFFF0000000000000, float [[extrct_5]]
45+
; CHECK: %31 = select i1 %24, float 0xFFF0000000000000, float [[extrct_6]]
46+
; CHECK: %32 = select i1 %20, float 0xFFF0000000000000, float [[extrct_7]]
3947

4048

4149
; ModuleID = 'reduced.ll'

‎IGC/Compiler/tests/IGCVectorizer/vectorizer-select-one-bool.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
;
77
;============================ end_copyright_notice =============================
88

9-
; REQUIRES: llvm-16-plus, debug, regkeys
9+
; REQUIRES: llvm-16-plus, regkeys
1010
; RUN: igc_opt -S --opaque-pointers --igc-vectorizer -dce --regkey=VectorizerAllowUniformSelect=1 --regkey=VectorizerAllowUniformCMP=1 --regkey=VectorizerDepWindowMultiplier=6 --regkey=VectorizerAllowSamePredSelect=1 < %s 2>&1 | FileCheck %s
1111

1212
; CHECK: %vectorized_select = select i1 false, <8 x float> {{.*}}, <8 x float> {{.*}}

‎IGC/Compiler/tests/IGCVectorizer/vectorizer-single-pred.ll‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,12 @@
1-
; REQUIRES: llvm-16-plus, debug, regkeys
1+
;=========================== begin_copyright_notice ============================
2+
;
3+
; Copyright (C) 2025 Intel Corporation
4+
;
5+
; SPDX-License-Identifier: MIT
6+
;
7+
;============================ end_copyright_notice =============================
8+
9+
; REQUIRES: llvm-16-plus, regkeys
210
; RUN: igc_opt -S --opaque-pointers --igc-vectorizer --regkey=VectorizerAllowUniformSelect=1 --regkey=VectorizerAllowUniformCMP=1 -dce --regkey=VectorizerLog=1 --regkey=VectorizerLogToErr=1 < %s 2>&1 | FileCheck %s
311

412
; CHECK: Slice: %tmp18 = select i1 %tmpCMP, float 0.000000e+00, float %vector_extract

‎IGC/Compiler/tests/IGCVectorizer/vectorizer-tricky-insert-placement.ll‎

Lines changed: 21 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,27 @@
77
;============================ end_copyright_notice =============================
88

99
; REQUIRES: regkeys
10-
; RUN: igc_opt -S --igc-vectorizer -dce --regkey=VectorizerAllowSelect=1 --regkey=VectorizerAllowCMP=1 --regkey=VectorizerAllowMAXNUM=1 --regkey=VectorizerAllowWAVEALL=1 < %s 2>&1 | FileCheck %s
10+
; RUN: igc_opt -S --igc-vectorizer -dce --regkey=VectorizerAllowSelect=1 --regkey=VectorizerAllowCMP=1 --regkey=VectorizerAllowMAXNUM=1 --regkey=VectorizerAllowWAVEALL=1 --regkey=VectorizerLog=1 --regkey=VectorizerLogToErr=1 < %s 2>&1 | FileCheck %s
11+
12+
; CHECK: Slice: %37 = icmp slt i32 %3, %.pn1482
13+
; CHECK-NEXT: Slice: %38 = icmp slt i32 %4, %.pn1482
14+
; CHECK-NEXT: Slice: %39 = icmp slt i32 %5, %.pn1482
15+
; CHECK-NEXT: Slice: %40 = icmp slt i32 %6, %.pn1482
16+
; CHECK-NEXT: Slice: %41 = icmp slt i32 %7, %.pn1482
17+
; CHECK-NEXT: Slice: %42 = icmp slt i32 %8, %.pn1482
18+
; CHECK-NEXT: Slice: %43 = icmp slt i32 %9, %.pn1482
19+
; CHECK-NEXT: Slice: %44 = icmp slt i32 %10, %.pn1482
20+
21+
; CHECK: User is not uniform: {{%.*}} = select i1 {{.*}}, float 0xFFF0000000000000
22+
; CHECK-NEXT: User is not uniform: {{%.*}} = select i1 {{.*}}, float 0xFFF0000000000000
23+
; CHECK-NEXT: User is not uniform: {{%.*}} = select i1 {{.*}}, float 0xFFF0000000000000
24+
; CHECK-NEXT: User is not uniform: {{%.*}} = select i1 {{.*}}, float 0xFFF0000000000000
25+
; CHECK-NEXT: User is not uniform: {{%.*}} = select i1 {{.*}}, float 0xFFF0000000000000
26+
; CHECK-NEXT: User is not uniform: {{%.*}} = select i1 {{.*}}, float 0xFFF0000000000000
27+
; CHECK-NEXT: User is not uniform: {{%.*}} = select i1 {{.*}}, float 0xFFF0000000000000
28+
; CHECK-NEXT: User is not uniform: {{%.*}} = select i1 {{.*}}, float 0xFFF0000000000000
29+
; CHECK-NEXT: Select is stub vectorized, not uniform
30+
1131

1232
; CHECK-LABEL: ._crit_edge333:
1333
; CHECK: [[VEC_BIN:%.*]] = fmul <8 x float> {{.*}}, <float 1.250000e-01, float 1.250000e-01, float 1.250000e-01, float 1.250000e-01, float 1.250000e-01, float 1.250000e-01, float 1.250000e-01, float 1.250000e-01>

‎IGC/Compiler/tests/Legalization/select-vector.ll‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,8 @@
66
;
77
;============================ end_copyright_notice =============================
88
;
9-
; RUN: igc_opt -igc-legalization -S -dce < %s | FileCheck %s
9+
; REQUIRES: regkeys
10+
; RUN: igc_opt -igc-legalization -S -dce --regkey=LegalizerScalarizeSelectInstructions=1 < %s | FileCheck %s
1011
; ------------------------------------------------
1112
; Legalization: select vector
1213
; ------------------------------------------------

‎IGC/common/igc_flags.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -994,9 +994,9 @@ DECLARE_IGC_REGKEY(bool, VectorizerAllowEXP2, true, "Allow EXP2 instructions ins
994994
DECLARE_IGC_REGKEY(bool, VectorizerAllowMAXNUM, true, "Allow MAXNUM instructions inside vectorizer", true)
995995
DECLARE_IGC_REGKEY(bool, VectorizerAllowWAVEALL, true, "Allow WAVEALL instructions inside vectorizer", true)
996996
DECLARE_IGC_REGKEY(bool, VectorizerAllowCMP, true, "Allow CMP instructions inside vectorizer", true)
997-
DECLARE_IGC_REGKEY(bool, VectorizerAllowUniformCMP, false, "Allow CMP instructions inside vectorizer", true)
997+
DECLARE_IGC_REGKEY(bool, VectorizerAllowUniformCMP, true, "Allow CMP instructions inside vectorizer", true)
998998
DECLARE_IGC_REGKEY(bool, VectorizerAllowSelect, true, "Allow Select instructions inside vectorizer", true)
999-
DECLARE_IGC_REGKEY(bool, VectorizerAllowUniformSelect, false, "Allow Select instructions inside vectorizer", true)
999+
DECLARE_IGC_REGKEY(bool, VectorizerAllowUniformSelect, true, "Allow Select instructions inside vectorizer", true)
10001000
DECLARE_IGC_REGKEY(bool, VectorizerAllowSamePredSelect, false, "Allow Select instructions with identical predicate inside vectorizer", true)
10011001
DECLARE_IGC_REGKEY(bool, VectorizerAllowFMADMatching, true,
10021002
"Allow FADD and FMUL instructions to be matched later in the pattern match pass", true)
@@ -1009,7 +1009,7 @@ DECLARE_IGC_REGKEY(
10091009
bool, VectorizerEnablePartialVectorization, true,
10101010
"Not fully tested option, allows to substitute scalar part with partially vectorized through extract elements",
10111011
true)
1012-
DECLARE_IGC_REGKEY(bool, LegalizerScalarizeSelectInstructions, true, "Ask legalizer to not scalarize vector typed selects", true)
1012+
DECLARE_IGC_REGKEY(bool, LegalizerScalarizeSelectInstructions, false, "Ask legalizer to not scalarize vector typed selects", true)
10131013
DECLARE_IGC_REGKEY(bool, DisableOCLScalarizer, false, "Disable ScalarizeFunction pass in OCL pipeline", true)
10141014
DECLARE_IGC_REGKEY(bool, DisablePHIScalarization, false, "Disable scalarization of PHINode instructions", true)
10151015
DECLARE_IGC_REGKEY(bool, EnableSelectiveScalarizer, false, "enable selective scalarizer on GPGPU path", true)

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