fpga_patch

diff -uprN openwifi-hw/boards/sdrpi/src/system.bd law_hw/boards/sdrpi/src/system.bd
--- openwifi-hw/boards/sdrpi/src/system.bd	2025-07-29 17:29:19.228495786 +0800
+++ law_hw/boards/sdrpi/src/system.bd	2025-07-29 17:55:21.344745906 +0800
@@ -4758,6 +4758,12 @@
               "dac_valid"
             ]
           },
+          "tx_intf_0_data": {
+            "ports": [
+              "tx_intf_0/data",
+              "xpu_0/data"
+            ]
+          },
           "tx_intf_0_data_to_acc": {
             "ports": [
               "tx_intf_0/data_to_acc",
@@ -4811,6 +4817,12 @@
               "xpu_0/phy_tx_start"
             ]
           },
+          "tx_intf_0_qos": {
+            "ports": [
+              "tx_intf_0/qos",
+              "xpu_0/qos"
+            ]
+          },
           "tx_intf_0_quit_retrans": {
             "ports": [
               "tx_intf_0/quit_retrans",
@@ -4823,6 +4835,18 @@
               "xpu_0/reset_backoff"
             ]
           },
+          "tx_intf_0_timestamp_limit": {
+            "ports": [
+              "tx_intf_0/timestamp_limit",
+              "xpu_0/timestamp_limit"
+            ]
+          },
+          "tx_intf_0_timestamp_reg": {
+            "ports": [
+              "tx_intf_0/timestamp_reg",
+              "xpu_0/slv_reg60"
+            ]
+          },
           "tx_intf_0_tx_hold": {
             "ports": [
               "tx_intf_0/tx_hold",
@@ -4866,6 +4890,12 @@
               "xpu_0/tx_ht_aggr"
             ]
           },
+          "tx_intf_0_use_retrans_limit": {
+            "ports": [
+              "tx_intf_0/use_retrans_limit",
+              "xpu_0/use_retrans_limit"
+            ]
+          },
           "xlconcat_0_dout": {
             "ports": [
               "xlconcat_0/dout",
diff -uprN openwifi-hw/ip/openwifi_ip.tcl law_hw/ip/openwifi_ip.tcl
--- openwifi-hw/ip/openwifi_ip.tcl	2025-07-29 17:29:19.236495684 +0800
+++ law_hw/ip/openwifi_ip.tcl	2025-07-29 17:35:37.675712824 +0800
@@ -337,6 +337,11 @@ proc create_hier_cell_openwifi_ip { pare
   connect_bd_net -net tx_intf_0_tx_hold [get_bd_pins openofdm_tx_0/result_iq_hold] [get_bd_pins tx_intf_0/tx_hold]
   connect_bd_net -net tx_intf_0_tx_iq_fifo_empty [get_bd_pins tx_intf_0/tx_iq_fifo_empty] [get_bd_pins xpu_0/tx_iq_fifo_empty]
   connect_bd_net -net tx_intf_0_tx_pkt_need_ack [get_bd_pins tx_intf_0/tx_pkt_need_ack] [get_bd_pins xpu_0/tx_pkt_need_ack]
+  connect_bd_net -net tx_intf_0_timestamp_limit [get_bd_pins tx_intf_0/timestamp_limit] [get_bd_pins xpu_0/timestamp_limit]
+  connect_bd_net -net tx_intf_0_timestamp_reg [get_bd_pins tx_intf_0/timestamp_reg] [get_bd_pins xpu_0/slv_reg60]
+  connect_bd_net -net tx_intf_0_qos [get_bd_pins tx_intf_0/qos] [get_bd_pins xpu_0/qos]
+  connect_bd_net -net tx_intf_0_data [get_bd_pins tx_intf_0/data] [get_bd_pins xpu_0/data]
+  connect_bd_net -net tx_intf_0_use_retrans_limit [get_bd_pins tx_intf_0/use_retrans_limit] [get_bd_pins xpu_0/use_retrans_limit]
   connect_bd_net -net tx_intf_0_tx_pkt_retrans_limit [get_bd_pins tx_intf_0/tx_pkt_retrans_limit] [get_bd_pins xpu_0/tx_pkt_retrans_limit]
   connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_0/Dout] [get_bd_pins xpu_0/ddc_i]
   connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_pins xpu_0/ddc_q]
diff -uprN openwifi-hw/ip/openwifi_ip_ultra_scale.tcl law_hw/ip/openwifi_ip_ultra_scale.tcl
--- openwifi-hw/ip/openwifi_ip_ultra_scale.tcl	2025-07-29 17:29:19.236495684 +0800
+++ law_hw/ip/openwifi_ip_ultra_scale.tcl	2025-07-29 17:35:50.271554443 +0800
@@ -358,6 +358,11 @@ proc create_hier_cell_openwifi_ip { pare
   connect_bd_net -net tx_intf_0_tx_itrpt [get_bd_pins tx_itrpt] [get_bd_pins tx_intf_0/tx_itrpt]
   connect_bd_net -net tx_intf_0_tx_itrpt_led [get_bd_pins led0] [get_bd_pins tx_intf_0/tx_itrpt_led]
   connect_bd_net -net tx_intf_0_tx_pkt_need_ack [get_bd_pins side_ch_0/tx_pkt_need_ack] [get_bd_pins tx_intf_0/tx_pkt_need_ack] [get_bd_pins xpu_0/tx_pkt_need_ack]
+  connect_bd_net -net tx_intf_0_timestamp_limit [get_bd_pins tx_intf_0/timestamp_limit] [get_bd_pins xpu_0/timestamp_limit]
+  connect_bd_net -net tx_intf_0_timestamp_reg [get_bd_pins tx_intf_0/timestamp_reg] [get_bd_pins xpu_0/slv_reg60]
+  connect_bd_net -net tx_intf_0_qos [get_bd_pins tx_intf_0/qos] [get_bd_pins xpu_0/qos]
+  connect_bd_net -net tx_intf_0_data [get_bd_pins tx_intf_0/data] [get_bd_pins xpu_0/data]
+  connect_bd_net -net tx_intf_0_use_retrans_limit [get_bd_pins tx_intf_0/use_retrans_limit] [get_bd_pins xpu_0/use_retrans_limit]
   connect_bd_net -net tx_intf_0_tx_pkt_retrans_limit [get_bd_pins tx_intf_0/tx_pkt_retrans_limit] [get_bd_pins xpu_0/tx_pkt_retrans_limit]
   connect_bd_net -net tx_intf_0_tx_queue_idx_reg [get_bd_pins side_ch_0/tx_queue_idx_reg] [get_bd_pins tx_intf_0/tx_queue_idx_reg]
   connect_bd_net -net tx_intf_0_tx_queue_idx_to_xpu [get_bd_pins tx_intf_0/tx_queue_idx_to_xpu] [get_bd_pins xpu_0/tx_queue_idx]
diff -uprN openwifi-hw/ip/tx_intf/src/tx_bit_intf.v law_hw/ip/tx_intf/src/tx_bit_intf.v
--- openwifi-hw/ip/tx_intf/src/tx_bit_intf.v	2025-07-29 17:29:19.236495684 +0800
+++ law_hw/ip/tx_intf/src/tx_bit_intf.v	2025-07-29 17:48:52.097691505 +0800
@@ -73,17 +73,24 @@
       `DEBUG_PREFIX output reg reset_backoff,
       `DEBUG_PREFIX output reg high_trigger,
       `DEBUG_PREFIX output reg [5:0] bd_wr_idx,
+      `DEBUG_PREFIX output reg [63:0] timestamp_limit,
+      `DEBUG_PREFIX output wire qos,
+      `DEBUG_PREFIX output wire data,
+      `DEBUG_PREFIX output wire use_retrans_limit,
       // output reg [15:0] tx_pkt_num_dma_byte,
       output wire [(WIFI_TX_BRAM_DATA_WIDTH-1):0] douta,
       output reg cts_toself_bb_is_ongoing,
       output reg cts_toself_rf_is_ongoing,
+      output reg [31:0] reg60,
+      output reg tx_drop,
 	    
 	    // port to phy_tx
 	    `DEBUG_PREFIX input wire tx_end_from_acc,
 	    output wire [(WIFI_TX_BRAM_DATA_WIDTH-1):0] bram_data_to_acc,
       input wire  [(WIFI_TX_BRAM_ADDR_WIDTH-1):0] bram_addr,
 
-      input wire tsf_pulse_1M
+      input wire tsf_pulse_1M,
+      input wire [63:0] tsf_runtime_val
 	);
     
     localparam [3:0]   WAIT_TO_TRIG=                    4'b0000,
@@ -97,7 +104,10 @@
                        DO_PHY_HDR1 =                    4'b1000,
                        DO_PHY_HDR2 =                    4'b1001,
                        DO_TX =                          4'b1010,
-                       WAIT_TX_COMP =                   4'b1011;
+                       WAIT_TX_COMP =                   4'b1011,
+                       JUDGE_DROP =                     4'b1100,
+                       DROP =                           4'b1101,
+                       DO_DROP =                        4'b1110;
     `DEBUG_PREFIX reg [3:0] high_tx_ctl_state;
     `DEBUG_PREFIX reg [3:0] high_tx_ctl_state_old;
     
@@ -114,17 +124,19 @@
     `DEBUG_PREFIX reg wea_internal;
     reg [12:0] addra_internal;
     reg [(C_S00_AXIS_TDATA_WIDTH-1):0] dina_internal;
+    reg [(C_S00_AXIS_TDATA_WIDTH-1):0] dina_drop;
 
     `DEBUG_PREFIX reg [3:0] floating_pkt_flag;
     
     `DEBUG_PREFIX reg [1:0] tx_queue_idx_reg;
-    `DEBUG_PREFIX wire [63:0] tx_config_fifo_rd_data0;
-    `DEBUG_PREFIX wire [63:0] tx_config_fifo_rd_data1;
-    `DEBUG_PREFIX wire [63:0] tx_config_fifo_rd_data2;
-    `DEBUG_PREFIX wire [63:0] tx_config_fifo_rd_data3;
-    reg [63:0] tx_config_current, tx_config_current_prev;
-    reg [63:0] tx_config_current_next [3:0];
-
+    `DEBUG_PREFIX wire [127:0] tx_config_fifo_rd_data0;
+    `DEBUG_PREFIX wire [127:0] tx_config_fifo_rd_data1;
+    `DEBUG_PREFIX wire [127:0] tx_config_fifo_rd_data2;
+    `DEBUG_PREFIX wire [127:0] tx_config_fifo_rd_data3;
+    reg [127:0] tx_config_current, tx_config_current_prev;
+    reg [127:0] tx_config_current_next [3:0];
+    reg [63:0] timestamp_start;
+ 
     wire [3:0] rate_signal_value;
     wire [3:0] cts_rate_signal_value;
     wire [15:0] cts_duration;
@@ -157,6 +169,9 @@
     assign use_ht_rate = phy_hdr_config_current[15];
     assign rate_hw_value = phy_hdr_config_current[19:16];
     assign ht_aggr_start = phy_hdr_config_current[20];
+    assign qos = phy_hdr_config_current[21];
+    assign data = phy_hdr_config_current[22];
+    assign use_retrans_limit = phy_hdr_config_current[23];
 
     reg [3:0] rate_legacy;
     reg [8:0] dbps_ht;
@@ -213,6 +228,8 @@
     reg start_delay3;
     reg start_delay4;
     reg start_delay5;
+    reg [31:0] tx;
+    reg [31:0] limit;
 
     `DEBUG_PREFIX reg tx_try_complete_dl0;
     `DEBUG_PREFIX reg tx_try_complete_dl1;
@@ -302,6 +319,7 @@
           wea_internal<=0;
           addra_internal<=0;
           dina_internal<=0;
+          dina_drop<=0;
 
           pkt_cnt <= 0;
           len_ht <= 0;
@@ -332,6 +350,9 @@
           reset_backoff<=0;
           high_trigger<=0;
           mac_addr_reg<=0;
+          reg60<=0;
+          tx <= 0;
+          limit <= 0;
         end                                                                   
       else begin
         high_tx_ctl_state_old <= high_tx_ctl_state;
@@ -350,6 +371,7 @@
 
             cts_toself_bb_is_ongoing<=0;
             cts_toself_rf_is_ongoing<=0;
+            tx_drop <= 0;
 
             read_from_s_axis_en <= 0;
             if ( slice_en[0] && (~tx_config_fifo_empty[0] || floating_pkt_flag[0]) && (~tx_bb_is_ongoing) && (~ack_tx_flag) && tx_control_state_idle && (~tx_try_complete_dl_pulses) && (~fcs_in_strobe_dl_pulses)) begin
@@ -460,17 +482,64 @@
             if(high_tx_ctl_state_old == WAIT_CHANCE) begin
               pkt_cnt <= 0;
               len_ht <= 0;
+              timestamp_limit <= tx_config_current[127:64] + 15 * 1000;
+              timestamp_start <= tx_config_current[127:64];
+              high_tx_ctl_state  <= JUDGE_DROP;
+            end else if (high_tx_ctl_state_old == CHECK_AGGR) begin
+              high_tx_ctl_state  <= PREPARE_TX_JUDGE;
+            end
+          end
+
+          JUDGE_DROP: begin
+            if (tsf_runtime_val >= timestamp_limit && (qos || data)) begin
+                high_tx_ctl_state  <= DROP;
+              //drop_count <= drop_count + 1;
+            end else begin
+              high_tx_ctl_state  <= PREPARE_TX_JUDGE;
             end
+          end
+
+          DROP: begin
+            // 802.11ag packets
+			      if(pkt_cnt == 0 && use_ht_rate == 0) begin
+				      len_pkt_sym <= (|len_psdu[2:0] == 0 ? (len_psdu>>3) : (len_psdu>>3)+1);
+
+			      // 802.11n packets
+			      end else begin
+					    // Non aggregation packet
+				    if(pkt_cnt == 0 && use_ht_aggr == 0) begin
+					    len_pkt_sym <= (|len_psdu[2:0] == 0 ? (len_psdu>>3) : (len_psdu>>3)+1);
+      			end else begin
+              len_pkt_sym <= len_psdu>>3;
+            end
+            end
+            wr_counter <= 2;
+			      read_from_s_axis_en <= 1;
+            high_tx_ctl_state<= DO_DROP;
+          end
+
+          DO_DROP: begin
+            dina_drop<=data_from_s_axis;
 
-            high_tx_ctl_state  <= PREPARE_TX_JUDGE;
+            wr_counter <= ( wea_high?(wr_counter + 1):wr_counter );
+            if (wr_counter == (2 + len_pkt_sym-1) || !emptyn_from_s_axis) begin
+              read_from_s_axis_en<= 0;
+              high_tx_ctl_state<= WAIT_TO_TRIG;
+              tx_drop <= 1;
+            end else begin
+              read_from_s_axis_en<= read_from_s_axis_en;
+              high_tx_ctl_state<= high_tx_ctl_state;
+            end
           end
 
           PREPARE_TX_JUDGE: begin
             if (use_cts_protect==1) begin // from cts_toself_config[31] in tx queue
               // read_from_s_axis_en <= read_from_s_axis_en;
               high_tx_ctl_state  <= DO_CTS_TOSELF;
+              //timestamp_limit <= tsf_runtime_val + 10 * 1000;
             end else begin
               high_tx_ctl_state  <= CHECK_AGGR;
+              //timestamp_limit <= tsf_runtime_val + 5 * 1000;
             end
           end
 
@@ -565,6 +634,12 @@
           end
 
           PREP_PHY_HDR: begin
+            if (pkt_cnt > 1) begin
+              timestamp_limit <= (tsf_runtime_val + 8 * 1000 > timestamp_start + 45 * 1000 ? timestamp_start + 45 * 1000 : tsf_runtime_val + 8 * 1000);
+            end else if (qos || data) begin
+              timestamp_limit <= (tsf_runtime_val + 3 * 1000 > timestamp_start + 15 * 1000 ? timestamp_start + 15 * 1000 : tsf_runtime_val + 3 * 1000);
+            end
+            //pkt_cnt <= pkt_cnt + drop_count;
 
 			// 802.11ag packets
 			if(use_ht_rate == 0) begin
@@ -665,6 +740,16 @@
           end
           
           DO_TX: begin
+            //drop_count <= 0;
+            if (high_tx_ctl_state_old == DO_PHY_HDR1 || high_tx_ctl_state_old == DO_PHY_HDR2) begin
+              tx <= tsf_runtime_val - timestamp_start;
+              limit <= timestamp_limit - timestamp_start;
+            end else if (high_tx_ctl_state_old == DO_TX) begin
+              reg60 <= {tx[15:0], limit[15:0]};
+            end  else begin
+              reg60 <= reg60;
+            end
+
             wea_internal<= wea_high;
             addra_internal<=wr_counter;
             dina_internal<=data_from_s_axis;
@@ -762,16 +847,16 @@
       .ECC_MODE("no_ecc"),       // String
       .FIFO_MEMORY_TYPE("auto"), // String
       .FIFO_READ_LATENCY(0),     // DECIMAL
-      .FIFO_WRITE_DEPTH(64),   // DECIMAL
+      .FIFO_WRITE_DEPTH(128),   // DECIMAL
       .FULL_RESET_VALUE(0),      // DECIMAL
       .PROG_EMPTY_THRESH(10),    // DECIMAL
       .PROG_FULL_THRESH(10),     // DECIMAL
       .RD_DATA_COUNT_WIDTH(7),   // DECIMAL
-      .READ_DATA_WIDTH(64),      // DECIMAL
+      .READ_DATA_WIDTH(128),      // DECIMAL
       .READ_MODE("fwft"),         // String
       .USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count
       .WAKEUP_TIME(0),           // DECIMAL
-      .WRITE_DATA_WIDTH(64),     // DECIMAL
+      .WRITE_DATA_WIDTH(128),     // DECIMAL
       .WR_DATA_COUNT_WIDTH(7)    // DECIMAL
     ) fifo64_1clk_dep64_i0 (
       .almost_empty(),
@@ -791,7 +876,7 @@
       .wr_ack(),
       .wr_data_count(),
       .wr_rst_busy(),
-      .din({cts_toself_config,tx_config}),
+      .din({tsf_runtime_val,cts_toself_config,tx_config}),
       .injectdbiterr(),
       .injectsbiterr(),
       .rd_en(tx_config_fifo_rden[0]),
@@ -850,16 +935,16 @@
       .ECC_MODE("no_ecc"),       // String
       .FIFO_MEMORY_TYPE("auto"), // String
       .FIFO_READ_LATENCY(0),     // DECIMAL
-      .FIFO_WRITE_DEPTH(64),   // DECIMAL
+      .FIFO_WRITE_DEPTH(128),   // DECIMAL
       .FULL_RESET_VALUE(0),      // DECIMAL
       .PROG_EMPTY_THRESH(10),    // DECIMAL
       .PROG_FULL_THRESH(10),     // DECIMAL
       .RD_DATA_COUNT_WIDTH(7),   // DECIMAL
-      .READ_DATA_WIDTH(64),      // DECIMAL
+      .READ_DATA_WIDTH(128),      // DECIMAL
       .READ_MODE("fwft"),         // String
       .USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count
       .WAKEUP_TIME(0),           // DECIMAL
-      .WRITE_DATA_WIDTH(64),     // DECIMAL
+      .WRITE_DATA_WIDTH(128),     // DECIMAL
       .WR_DATA_COUNT_WIDTH(7)    // DECIMAL
     ) fifo64_1clk_dep64_i1 (
       .almost_empty(),
@@ -879,7 +964,7 @@
       .wr_ack(),
       .wr_data_count(),
       .wr_rst_busy(),
-      .din({cts_toself_config,tx_config}),
+      .din({tsf_runtime_val,cts_toself_config,tx_config}),
       .injectdbiterr(),
       .injectsbiterr(),
       .rd_en(tx_config_fifo_rden[1]),
@@ -938,16 +1023,16 @@
       .ECC_MODE("no_ecc"),       // String
       .FIFO_MEMORY_TYPE("auto"), // String
       .FIFO_READ_LATENCY(0),     // DECIMAL
-      .FIFO_WRITE_DEPTH(64),   // DECIMAL
+      .FIFO_WRITE_DEPTH(128),   // DECIMAL
       .FULL_RESET_VALUE(0),      // DECIMAL
       .PROG_EMPTY_THRESH(10),    // DECIMAL
       .PROG_FULL_THRESH(10),     // DECIMAL
       .RD_DATA_COUNT_WIDTH(7),   // DECIMAL
-      .READ_DATA_WIDTH(64),      // DECIMAL
+      .READ_DATA_WIDTH(128),      // DECIMAL
       .READ_MODE("fwft"),         // String
       .USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count
       .WAKEUP_TIME(0),           // DECIMAL
-      .WRITE_DATA_WIDTH(64),     // DECIMAL
+      .WRITE_DATA_WIDTH(128),     // DECIMAL
       .WR_DATA_COUNT_WIDTH(7)    // DECIMAL
     ) fifo64_1clk_dep64_i2 (
       .almost_empty(),
@@ -967,7 +1052,7 @@
       .wr_ack(),
       .wr_data_count(),
       .wr_rst_busy(),
-      .din({cts_toself_config,tx_config}),
+      .din({tsf_runtime_val,cts_toself_config,tx_config}),
       .injectdbiterr(),
       .injectsbiterr(),
       .rd_en(tx_config_fifo_rden[2]),
@@ -1026,16 +1111,16 @@
       .ECC_MODE("no_ecc"),       // String
       .FIFO_MEMORY_TYPE("auto"), // String
       .FIFO_READ_LATENCY(0),     // DECIMAL
-      .FIFO_WRITE_DEPTH(64),   // DECIMAL
+      .FIFO_WRITE_DEPTH(128),   // DECIMAL
       .FULL_RESET_VALUE(0),      // DECIMAL
       .PROG_EMPTY_THRESH(10),    // DECIMAL
       .PROG_FULL_THRESH(10),     // DECIMAL
       .RD_DATA_COUNT_WIDTH(7),   // DECIMAL
-      .READ_DATA_WIDTH(64),      // DECIMAL
+      .READ_DATA_WIDTH(128),      // DECIMAL
       .READ_MODE("fwft"),         // String
       .USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count
       .WAKEUP_TIME(0),           // DECIMAL
-      .WRITE_DATA_WIDTH(64),     // DECIMAL
+      .WRITE_DATA_WIDTH(128),     // DECIMAL
       .WR_DATA_COUNT_WIDTH(7)    // DECIMAL
     ) fifo64_1clk_dep64_i3 (
       .almost_empty(),
@@ -1055,7 +1140,7 @@
       .wr_ack(),
       .wr_data_count(),
       .wr_rst_busy(),
-      .din({cts_toself_config,tx_config}),
+      .din({tsf_runtime_val,cts_toself_config,tx_config}),
       .injectdbiterr(),
       .injectsbiterr(),
       .rd_en(tx_config_fifo_rden[3]),
diff -uprN openwifi-hw/ip/tx_intf/src/tx_interrupt_selection.v law_hw/ip/tx_intf/src/tx_interrupt_selection.v
--- openwifi-hw/ip/tx_intf/src/tx_interrupt_selection.v	2025-07-29 17:29:19.236495684 +0800
+++ law_hw/ip/tx_intf/src/tx_interrupt_selection.v	2025-07-29 17:42:35.094455149 +0800
@@ -13,6 +13,7 @@ module tx_interrupt_selection
      input wire tx_start_from_acc,
      input wire tx_end_from_acc,
      input wire tx_try_complete,
+     input wire tx_drop,
 
      // to ps interrupt
      output reg tx_itrpt
@@ -34,7 +35,7 @@ begin
                     tx_itrpt = tx_end_from_acc;
                end
      3'b100 : begin
-                    tx_itrpt = tx_try_complete;
+                    tx_itrpt = tx_try_complete | tx_drop;
                end
      default: begin
                     tx_itrpt = 0;
diff -uprN openwifi-hw/ip/tx_intf/src/tx_intf.v law_hw/ip/tx_intf/src/tx_intf.v
--- openwifi-hw/ip/tx_intf/src/tx_intf.v	2025-07-29 17:29:19.240495634 +0800
+++ law_hw/ip/tx_intf/src/tx_intf.v	2025-07-29 17:52:26.726966786 +0800
@@ -114,6 +114,7 @@ module tx_intf #
   output wire reset_backoff,
   output wire high_trigger,
   output wire [1:0] tx_queue_idx_to_xpu,
+  output wire [63:0] timestamp_limit,
 
   // Ports of Axi Slave Bus Interface S00_AXI
   input wire  s00_axi_aclk,
@@ -146,7 +147,12 @@ module tx_intf #
   input wire [(C_S00_AXIS_TDATA_WIDTH/8)-1 : 0] s00_axis_tstrb,
   input wire  s00_axis_tlast,
   input wire  s00_axis_tvalid,
-  input wire [63:0] tsf_runtime_val
+  input wire [63:0] tsf_runtime_val,
+  output wire qos,
+  output wire data,
+  output wire use_retrans_limit,
+  output wire tx_drop,
+  output wire [31:0] timestamp_reg
 );
 
 	function integer clogb2 (input integer bit_depth);                                   
@@ -463,6 +469,7 @@ module tx_intf #
     .tx_start_from_acc(tx_start_from_acc),
     .tx_end_from_acc(tx_end_from_acc),
     .tx_try_complete(tx_try_complete),
+    .tx_drop(tx_drop),
 
     // to ps interrupt
     .tx_itrpt(tx_itrpt_internal)
@@ -529,13 +536,20 @@ module tx_intf #
         .douta(douta),
         .cts_toself_bb_is_ongoing(cts_toself_bb_is_ongoing),
         .cts_toself_rf_is_ongoing(cts_toself_rf_is_ongoing),
+
+        .timestamp_limit(timestamp_limit),
+        .qos(qos),
+        .data(data),
+        .use_retrans_limit(use_retrans_limit),
+        .reg60(timestamp_reg),
          
          // to send out to wifi tx module
         .tx_end_from_acc(tx_end_from_acc),
         .bram_data_to_acc(data_to_acc),
         .bram_addr(bram_addr),
 
-        .tsf_pulse_1M(tsf_pulse_1M)
+        .tsf_pulse_1M(tsf_pulse_1M),
+        .tsf_runtime_val(tsf_runtime_val)
     );
 
     tx_iq_intf # (
diff -uprN openwifi-hw/ip/xpu/src/tx_control.v law_hw/ip/xpu/src/tx_control.v
--- openwifi-hw/ip/xpu/src/tx_control.v	2025-07-29 17:29:19.240495634 +0800
+++ law_hw/ip/xpu/src/tx_control.v	2025-07-29 17:53:44.829973710 +0800
@@ -29,6 +29,8 @@
         input wire [3:0] max_num_retrans,
         input wire tx_pkt_need_ack,
         input wire [3:0] tx_pkt_retrans_limit,
+        input wire [63:0] timestamp_limit,
+        input wire [63:0] tsf_runtime_val,
         input wire tx_ht_aggr,
         `DEBUG_PREFIX input wire [6:0]  relative_decoding_latency,
         `DEBUG_PREFIX input wire [14:0] send_ack_wait_top,
@@ -57,6 +59,9 @@
         input wire cts_toself_bb_is_ongoing,//this should rise before the phy tx end valid of phy tx IP core.
         `DEBUG_PREFIX input wire backoff_done,
         input wire [(WIFI_TX_BRAM_ADDR_WIDTH-1):0] bram_addr,
+        input wire qos,
+        input wire data,
+        input wire use_retrans_limit,
 
         input wire ampdu_rx_tid_disable,
         input wire [3:0] ampdu_rx_tid,
@@ -85,7 +90,8 @@
         `DEBUG_PREFIX output reg ack_tx_flag,
         `DEBUG_PREFIX output reg wea,
         `DEBUG_PREFIX output reg [9:0] addra,
-        output reg [(C_S00_AXIS_TDATA_WIDTH-1):0] dina
+        output reg [(C_S00_AXIS_TDATA_WIDTH-1):0] dina,
+        output reg [31:0] slv_reg61
 	);
 
   localparam [3:0]    IDLE =                     4'b0000,
@@ -157,6 +163,8 @@
   reg [14:0] recv_ack_sig_valid_timeout_top_scale;
   reg [14:0] recv_ack_timeout_top_adj_scale;
   `DEBUG_PREFIX reg retrans_started;
+  reg [63:0] interval1;
+  reg [63:0] interval2;
 
   assign tx_control_state_idle =((tx_control_state==IDLE) && (~retrans_started));
 
@@ -248,6 +256,8 @@
           send_ack_wait_top_scale_lock <=0;
           recv_ack_sig_valid_timeout_top_scale <= 0;
           recv_ack_timeout_top_adj_scale <= 0;
+          interval1 <= 0;
+          interval2 <= 0;
         end
       else begin
         tx_control_state_old<=tx_control_state;
@@ -303,6 +313,11 @@
             // retrans_in_progress<=retrans_in_progress;
             bitmap_count <= 0;
 
+            if (tx_try_complete == 1) begin
+              interval1 <= 0;
+              interval2 <= 0;
+            end
+
             // This is the last packet of aggregation and fcs valid
             if ( rx_ht_aggr_last && fcs_valid && is_qosdata && (self_mac_addr==addr1) && (ampdu_rx_tid == qos_tid || ampdu_rx_tid_disable) )
               begin
@@ -356,6 +371,14 @@
                   retrans_started<=0;
                   if (tx_pkt_need_ack==1) // continue to actual ACK receiving
                       begin
+                      if (interval1==0) begin
+                          interval1 <= tsf_runtime_val - timestamp_limit + 50*1000;
+                        end else if (interval2==0) begin
+                          interval2 <= tsf_runtime_val - timestamp_limit + 50*1000;
+                        end else begin
+                          interval1 <= interval2;
+                          interval2 <= tsf_runtime_val - timestamp_limit + 50*1000;
+                        end
                       tx_control_state<= RECV_ACK_WAIT_TX_BB_DONE;
                       addra<=2;
                       tx_try_complete<=0;
@@ -500,6 +523,7 @@
             // recv_ack_timeout_top<=recv_ack_timeout_top;
 
             // addra<=addra;
+            slv_reg61 <= {interval1[15:0],interval2[15:0]};
 
             tx_dpram_op_counter <= ( tx_dpram_op_counter!=3?(tx_dpram_op_counter + 1):tx_dpram_op_counter );
             if(tx_ht_aggr==0 && tx_dpram_op_counter==2) begin
@@ -537,9 +561,22 @@
             // ack_addr <= ack_addr;
             // tx_dpram_op_counter<=tx_dpram_op_counter;
             // recv_ack_timeout_top<=recv_ack_timeout_top;
-
             ack_timeout_count<= ( (sig_valid && (signal_len==14||signal_len==32))?0:(ack_timeout_count+1) );
-            if ( (ack_timeout_count<recv_ack_sig_valid_timeout_top_scale) && sig_valid && (signal_len==14||signal_len==32) ) begin //before timeout, we detect a sig valid, signal length field is ACK/BLK_ACK
+
+            if (tsf_runtime_val >= timestamp_limit && (qos || data)) begin
+                tx_control_state<= IDLE;
+                tx_try_complete<=1;
+                // tx_status<={1'b1,num_retrans};
+                num_retrans_lock <= num_retrans;
+                blk_ack_resp_ssn_lock <= 0;
+                blk_ack_bitmap_lock <= 0;
+                num_retrans<=0;
+                // start_retrans<=start_retrans;
+                retrans_in_progress<=0;
+            end
+
+            // ack_timeout_count<= ( (sig_valid && (signal_len==14||signal_len==32))?0:(ack_timeout_count+1) );
+            else if ( (ack_timeout_count<recv_ack_sig_valid_timeout_top_scale) && sig_valid && (signal_len==14||signal_len==32) ) begin //before timeout, we detect a sig valid, signal length field is ACK/BLK_ACK
                 tx_control_state<= RECV_ACK;
                 // tx_try_complete<=tx_try_complete;
                 // tx_status<=tx_status;
@@ -553,21 +590,40 @@
                    recv_ack_timeout_top <= (({4'd12,2'd0})*`NUM_CLK_PER_US)+recv_ack_timeout_top_adj_scale;	// blk_ack_resp uses 12 ofdm symbols at 6Mbps
             end else if ( ack_timeout_count==recv_ack_sig_valid_timeout_top_scale ) begin // sig valid timeout
                 tx_control_state<= IDLE;
-                if  ((num_retrans==retrans_limit) || (retrans_limit==0)) begin// should not run into this state. but just in case
-                    tx_try_complete<=1;
-                    // tx_status<={1'b1,num_retrans};
-                    num_retrans_lock <= num_retrans;
-                    blk_ack_resp_ssn_lock <= 0;
-                    blk_ack_bitmap_lock <= 0;
-                    num_retrans<=0;
-                    // start_retrans<=start_retrans;
-                    retrans_in_progress<=0;
+                if (num_retrans == 8)  begin
+                  tx_try_complete<=1;
+                  num_retrans_lock <= num_retrans;
+                  blk_ack_resp_ssn_lock <= 0;
+                  blk_ack_bitmap_lock <= 0;
+                  num_retrans<=0;
+                  retrans_in_progress<=0;
+                end else if (use_retrans_limit && ((num_retrans==retrans_limit) || (retrans_limit==0)) && (qos || data)) begin
+                  tx_try_complete<=1;
+                  num_retrans_lock <= num_retrans;
+                  blk_ack_resp_ssn_lock <= 0;
+                  blk_ack_bitmap_lock <= 0;
+                  num_retrans<=0;
+                  retrans_in_progress<=0;
+                end else if (qos || data) begin
+                  num_retrans<=num_retrans+1;
+                  retrans_trigger<=1;
                 end else begin
-                    // tx_try_complete<=tx_try_complete;
-                    // tx_status<=tx_status;
-                    num_retrans<=num_retrans+1;
-                    retrans_trigger<=1;// start retransmission if ack did not arrive in time --
-                    // retrans_in_progress<=retrans_in_progress;
+                  if  ((num_retrans==retrans_limit) || (retrans_limit==0)) begin// should not run into this state. but just in case
+                      tx_try_complete<=1;
+                      // tx_status<={1'b1,num_retrans};
+                      num_retrans_lock <= num_retrans;
+                      blk_ack_resp_ssn_lock <= 0;
+                      blk_ack_bitmap_lock <= 0;
+                      num_retrans<=0;
+                      // start_retrans<=start_retrans;
+                      retrans_in_progress<=0;
+                  end else begin
+                      // tx_try_complete<=tx_try_complete;
+                      // tx_status<=tx_status;
+                      num_retrans<=num_retrans+1;
+                      retrans_trigger<=1;// start retransmission if ack did not arrive in time --
+                      // retrans_in_progress<=retrans_in_progress;
+                  end
                 end
             end 
             // else begin
@@ -589,10 +645,22 @@
             // ack_addr <= ack_addr;
             // tx_dpram_op_counter<=tx_dpram_op_counter;
             // recv_ack_timeout_top <= recv_ack_timeout_top;
-
             ack_timeout_count<=ack_timeout_count+1;
+            if (tsf_runtime_val >= timestamp_limit && (qos || data)) begin
+                tx_control_state<= IDLE;
+                tx_try_complete<=1;
+                // tx_status<={1'b1,num_retrans};
+                num_retrans_lock <= num_retrans;
+                blk_ack_resp_ssn_lock <= 0;
+                blk_ack_bitmap_lock <= 0;
+                num_retrans<=0;
+                // start_retrans<=start_retrans;
+                retrans_in_progress<=0;
+            end
+
+            // ack_timeout_count<=ack_timeout_count+1;
             // Detection of a normal ack packet is sufficient to acknowledge a traffic. However for aggregation traffic, a valid block ack response is required.
-            if ( (ack_timeout_count<recv_ack_timeout_top) && (((recv_ack_fcs_valid_disable|fcs_in_strobe) && is_ack) || (fcs_valid && is_blockackresp)) && (self_mac_addr==addr1)) begin//before timeout, we detect a ACK type frame fcs valid
+            else if ( (ack_timeout_count<recv_ack_timeout_top) && (((recv_ack_fcs_valid_disable|fcs_in_strobe) && is_ack) || (fcs_valid && is_blockackresp)) && (self_mac_addr==addr1)) begin//before timeout, we detect a ACK type frame fcs valid
                 tx_control_state<= IDLE;
                 tx_try_complete<=1;
                 // tx_status<={1'b0,num_retrans};
@@ -609,23 +677,42 @@
                 retrans_in_progress<=0;
             end else if ( ack_timeout_count==recv_ack_timeout_top ) begin// timeout
                 tx_control_state<= IDLE;
-                if  ((num_retrans==retrans_limit) || (retrans_limit==0)) begin// should not run into this state. but just in case
-                    tx_try_complete<=1;
-                    // tx_status<={1'b1,num_retrans};
-                    num_retrans_lock <= num_retrans;
-                    blk_ack_resp_ssn_lock <= 0;
-                    blk_ack_bitmap_lock <= 0;
-                    num_retrans<=0;
-                    // start_retrans<=start_retrans;
-                    retrans_in_progress<=0;
+                if (num_retrans == 8)  begin
+                  tx_try_complete<=1;
+                  num_retrans_lock <= num_retrans;
+                  blk_ack_resp_ssn_lock <= 0;
+                  blk_ack_bitmap_lock <= 0;
+                  num_retrans<=0;
+                  retrans_in_progress<=0;
+                end else if (use_retrans_limit && ((num_retrans==retrans_limit) || (retrans_limit==0)) && (qos || data)) begin
+                  tx_try_complete<=1;
+                  num_retrans_lock <= num_retrans;
+                  blk_ack_resp_ssn_lock <= 0;
+                  blk_ack_bitmap_lock <= 0;
+                  num_retrans<=0;
+                  retrans_in_progress<=0;
+                end else if (qos || data) begin
+                  num_retrans<=num_retrans+1;
+                  retrans_trigger<=1;
                 end else begin
-                    // tx_try_complete<=tx_try_complete;
-                    // tx_status<=tx_status;
-                    num_retrans<=num_retrans+1;
-                    retrans_trigger<=1; // start retranmission if ack did not receive in time -- 
-                    // retrans_in_progress<=retrans_in_progress;
-                end
-            end 
+                  if  ((num_retrans==retrans_limit) || (retrans_limit==0)) begin// should not run into this state. but just in case
+                      tx_try_complete<=1;
+                      // tx_status<={1'b1,num_retrans};
+                      num_retrans_lock <= num_retrans;
+                      blk_ack_resp_ssn_lock <= 0;
+                      blk_ack_bitmap_lock <= 0;
+                      num_retrans<=0;
+                      // start_retrans<=start_retrans;
+                      retrans_in_progress<=0;
+                  end else begin
+                      // tx_try_complete<=tx_try_complete;
+                      // tx_status<=tx_status;
+                      num_retrans<=num_retrans+1;
+                      retrans_trigger<=1;// start retransmission if ack did not arrive in time --
+                      // retrans_in_progress<=retrans_in_progress;
+                  end
+                end 
+            end
             // else begin
             //     tx_control_state<= tx_control_state;
             //     tx_try_complete<=tx_try_complete;
diff -uprN openwifi-hw/ip/xpu/src/xpu_s_axi.v law_hw/ip/xpu/src/xpu_s_axi.v
--- openwifi-hw/ip/xpu/src/xpu_s_axi.v	2025-07-29 17:29:19.240495634 +0800
+++ law_hw/ip/xpu/src/xpu_s_axi.v	2025-07-29 17:42:45.906318727 +0800
@@ -78,8 +78,8 @@
 		input  wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG57,
         input  wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG58,
         input  wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG59,
-        //input  wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG60,
-        //input  wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG61,
+        input  wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG60,
+        input  wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG61,
         input  wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG62,
         input  wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG63,
 		// User ports ends
@@ -230,8 +230,8 @@
 	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg57;
 	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg58;
 	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg59;
-	// reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg60;
-	// reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg61;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg60;
+	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg61;
 	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg62;
 	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg63;
 	wire	 slv_reg_rden;
@@ -1003,8 +1003,8 @@
 	        6'h39   : reg_data_out <= slv_reg57;
 	        6'h3A   : reg_data_out <= slv_reg58;
 	        6'h3B   : reg_data_out <= slv_reg59;
-	        //6'h3C   : reg_data_out <= slv_reg60;
-	        //6'h3D   : reg_data_out <= slv_reg61;
+	        6'h3C   : reg_data_out <= slv_reg60;
+	        6'h3D   : reg_data_out <= slv_reg61;
 	        6'h3E   : reg_data_out <= slv_reg62;
 	        6'h3F   : reg_data_out <= slv_reg63;
 	        default : reg_data_out <= 0;
@@ -1047,8 +1047,8 @@
           slv_reg57 <= 32'h0;
           slv_reg58 <= 32'h0;
           slv_reg59 <= 32'h0;
-          //slv_reg60 <= 32'h0;
-          //slv_reg61 <= 32'h0;
+          slv_reg60 <= 32'h0;
+          slv_reg61 <= 32'h0;
           slv_reg62 <= 32'h0;
           slv_reg63 <= 32'h0;
         end 
@@ -1066,8 +1066,8 @@
           slv_reg57 <= SLV_REG57;
           slv_reg58 <= SLV_REG58;
           slv_reg59 <= SLV_REG59;
-          //slv_reg60 <= SLV_REG60;
-          //slv_reg61 <= SLV_REG61;
+          slv_reg60 <= SLV_REG60;
+          slv_reg61 <= SLV_REG61;
           slv_reg62 <= SLV_REG62;
           slv_reg63 <= SLV_REG63;
         end 
diff -uprN openwifi-hw/ip/xpu/src/xpu.v law_hw/ip/xpu/src/xpu.v
--- openwifi-hw/ip/xpu/src/xpu.v	2025-07-29 17:29:19.240495634 +0800
+++ law_hw/ip/xpu/src/xpu.v	2025-07-29 17:47:11.274966775 +0800
@@ -94,6 +94,7 @@ module xpu #
   output wire [(C_S00_AXIS_TDATA_WIDTH-1):0] dina,
   input  wire tx_pkt_need_ack,
   input  wire [3:0] tx_pkt_retrans_limit,
+  input wire [63:0] timestamp_limit,
   input  wire tx_ht_aggr,
   input  wire [(WIFI_TX_BRAM_DATA_WIDTH-1):0] douta,//from dpram of tx_intf, for tx_control changing some bits to indicate it is the 1st pkt or retransmitted pkt
   input  wire cts_toself_bb_is_ongoing,//this should rise before the phy tx end valid of phy tx IP core to avoid tx_control waiting ack for this tx
@@ -108,6 +109,11 @@ module xpu #
   output wire [3:0] cw,
   input wire high_trigger,
   input wire [1:0] tx_queue_idx,
+  input wire qos,
+  input wire data,
+  input wire use_retrans_limit,
+  input wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg60,
+  output wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg61,
 
   // to side channel
   output wire [31:0] FC_DI,
@@ -548,6 +554,12 @@ module xpu #
     .max_num_retrans(max_num_retrans),
     .tx_pkt_need_ack(tx_pkt_need_ack&(~ack_rx_disable)),
     .tx_pkt_retrans_limit(tx_pkt_retrans_limit),
+    .timestamp_limit(timestamp_limit),
+    .tsf_runtime_val(tsf_runtime_val),
+    .qos(qos),
+    .data(data),
+    .use_retrans_limit(use_retrans_limit),
+    .slv_reg61(slv_reg61),
     .tx_ht_aggr(tx_ht_aggr),
     .relative_decoding_latency(relative_decoding_latency),
     .send_ack_wait_top(send_ack_wait_top),
@@ -856,8 +868,8 @@ xpu_s_axi # (
   .SLV_REG57(slv_reg57),
   .SLV_REG58(slv_reg58),
   .SLV_REG59(slv_reg59),
-  //.SLV_REG60(slv_reg60),
-  //.SLV_REG61(slv_reg61),
+  .SLV_REG60(slv_reg60),
+  .SLV_REG61(slv_reg61),
   .SLV_REG62(slv_reg62),
   .SLV_REG63(slv_reg63)
 );